Hi Varun, I am afraid, it is not possible to estimate the total number of WriteReq just by looking at the L2 cache statistics. You should see 1 ReadExReq in the L2 cache for every WriterReq that misses in the dcache but there won't be L2 requests for WriteReq that hit (including MSHR hits) in the cache.
Regards, Nikos On 21/01/2019 09:38, Varun Venkitaraman wrote: > Hi Nikos, > > Thanks for your valuable feedback. My major concern is how do I > understand total number of writes in L2 cache. I would really appreciate > if anyone can help me understand that. > > -- > With Regards, > Varun Venkitaraman. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
