Hi All, I have been generating elastic traces based on the instructions given on the http://gem5.org/TraceCPU and then replaying them for Low Power DDR models:
1. Elastic trace Generation: ./build/ARM/gem5.opt -d <out_dir> ./config/examples/se.py --cpu-type=O3_ARM_v7a_3 --caches --cmd=<binary location> --data-trace-file=deptrace.proto.gz --inst-trace-file=fetchtrace.proto.gz --mem-type=SimpleMemory 1. Elastic trace Replay: ./build/ARM/gem5.opt -d <out_dir> ./config/examples/etrace_replay.py --cpu-type=TraceCPU --caches --data-trace-file=<location of deptrace.proto.gz> --inst-trace-file=<location of fetchtrace.proto.gz> --mem-type=<LPDDR model> 1. Baseline Simulation: ./build/ARM/gem5.opt -d <out_dir> ./config/examples/se.py --cpu-type=O3_ARM_v7a_3 --caches --cmd=<binary location> --mem-type=<LPDDR model> When comparing the results from the replay with the baseline, I see a significant variance in multiple key metrics (CPI, system.mem_ctrls.bw*, etc.). There is a CPI variance of 40-60% and other mem_ctrl BW metrics see an even higher variance. This variance is seen for both LLVM Stanford test-cases as well as for SPEC benchmarks. I noticed that the sim_seconds for the replay is significantly shorter for the replay simulations (20% of baseline) which I feel could be the cause of the high variance. As a potential solution, I increased the memory latency for the etrace generation from 1ns to 45ns which is closer to the slower LPDDR memories. This instantly improved results bringing down the variance between baseline and replay simulations to within 10%. I know that we want to keep the memory latency down to the minimal to keep it from affecting the COMP_DELAY, so I am not sure if increasing this latency should affect the results as I see them. If I should not increase the memory latency, what else can I do to get more accurate results from the replayed simulations? Thanks, Sharookh Daruwalla
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