Hi everyone,
I have started working with gem5 from past 2 weeks and am trying to
simulate a multi-core CPU system with RISC-V ISA on gem5.
I have written a C file where I use inline assembly snippet to grab the
value of mhartid (Hardware Thread id), marchid and mstatus.
I used this command to statically compile C code: $
riscv64-unknown-elf-gcc-7.2.0 -static hello1.c
The C code is available at (hello1.c) https://pastebin.com/t5XBBWEz.
I have written my multi-core python configuration code: where the system
has two CPU cores, each having a private
I cache and D cache. These cache memories are connected to shared L2 cache
via L2 bus. The L2 cache memory
is connected to the memory controller via membus.
The code is attached or available at (python configuration file)
https://pastebin.com/utxxNfJg
I used the cache python file which Jason has provided as part of
learning-gem5 book. ((python cache file) https://pastebin.com/sTc8vwdh)
The command used to simulate on gem5: $ build/RISCV/gem5.opt
configs/multi_core/two_core/two_core_copy.py
After running this command, I get the console log : (console log without
loop) https://pastebin.com/t8rM9thk
>From this log, I am able to get the values as follows:
CPU1:
mhartid = 0
marchid = 8192
mstatus = 0
CPU2:
mhartid = 0
marchid = 8192
mstatus = 0
I strongly feel that mhartid of each processor should be different. Can
someone explain to me why they are the same?
Out of curiosity, I had put a loop in the C code to observe cache misses!
(please uncomment the loop in above C code to run! )
Again, I compiled the C code using the above command and simulated using
gem5.
I get a long message starting with "panic: Page table fault when accessing
virtual address 0x8000000000000000".
(console log with loop) https://pastebin.com/0xNyGkCE
Also, my max_miss_count parameter in config.ini remains to be 0 for all
caches.
I am unable to understand this error?
Other than this, may someone guide me to the steps of finding memory trace
and instruction trace for a binary executed on gem5 in RISC-V isa.
Thanks and regards,
Rishabh Jain
# -*- coding: utf-8 -*-
# Copyright (c) 2015 Jason Power
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Jason Power
""" Caches with options for a simple gem5 configuration script
This file contains L1 I/D and L2 caches to be used in the simple
gem5 configuration script. It uses the SimpleOpts wrapper to set up command
line options from each individual class.
"""
import m5
from m5.objects import Cache
# Add the common scripts to our path
m5.util.addToPath('../../')
from common import SimpleOpts
# Some specific options for caches
# For all options see src/mem/cache/BaseCache.py
class L1Cache(Cache):
"""Simple L1 Cache with default values"""
assoc = 2
tag_latency = 2
data_latency = 2
response_latency = 2
mshrs = 4
tgts_per_mshr = 20
def __init__(self, options=None):
super(L1Cache, self).__init__()
pass
def connectBus(self, bus):
"""Connect this cache to a memory-side bus"""
self.mem_side = bus.slave
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU-side port
This must be defined in a subclass"""
raise NotImplementedError
class L1ICache(L1Cache):
"""Simple L1 instruction cache with default values"""
# Set the default size
size = '16kB'
SimpleOpts.add_option('--l1i_size',
help="L1 instruction cache size. Default: %s" % size)
def __init__(self, opts=None):
super(L1ICache, self).__init__(opts)
if not opts or not opts.l1i_size:
return
self.size = opts.l1i_size
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU icache port"""
self.cpu_side = cpu.icache_port
class L1DCache(L1Cache):
"""Simple L1 data cache with default values"""
# Set the default size
size = '64kB'
SimpleOpts.add_option('--l1d_size',
help="L1 data cache size. Default: %s" % size)
def __init__(self, opts=None):
super(L1DCache, self).__init__(opts)
if not opts or not opts.l1d_size:
return
self.size = opts.l1d_size
def connectCPU(self, cpu):
"""Connect this cache's port to a CPU dcache port"""
self.cpu_side = cpu.dcache_port
class L2Cache(Cache):
"""Simple L2 Cache with default values"""
# Default parameters
size = '256kB'
assoc = 8
tag_latency = 20
data_latency = 20
response_latency = 20
mshrs = 20
tgts_per_mshr = 12
SimpleOpts.add_option('--l2_size', help="L2 cache size. Default: %s" % size)
def __init__(self, opts=None):
super(L2Cache, self).__init__()
if not opts or not opts.l2_size:
return
self.size = opts.l2_size
def connectCPUSideBus(self, bus):
self.cpu_side = bus.master
def connectMemSideBus(self, bus):
self.mem_side = bus.slave
from __future__ import print_function
import m5
import sys
from m5.objects import *
m5.util.addToPath('../../')
from caches import *
from common import SimpleOpts
# Set the usage message to display
SimpleOpts.set_usage("usage: %prog [options] <binary to execute>")
# Finalize the arguments and grab the opts so we can pass it on to our objects
(opts, args) = SimpleOpts.parse_args()
# get ISA for the default binary to run. This is mostly for simple testing
isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
# Default to running 'hello', use the compiled ISA to find the binary
binary = 'tests/test-progs/hello/bin/' + isa + '/linux/a.out'
# Check if there was a binary passed in via the command line and error if
# there are too many arguments
if len(args) == 1:
binary = args[0]
elif len(args) > 1:
SimpleOpts.print_help()
m5.fatal("Expected a binary to execute as positional argument")
print("Version of python is :::::::::::: " + sys.version)
#system config
system = System(cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(2)])
for i in range(2):
print([TimingSimpleCPU(cpu_id=i)])
for i in xrange(2):
print(system.cpu[i])
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
system.mem_mode = 'timing'
system.mem_ranges = [AddrRange('512MB')]
system.cpu_voltage_domain = VoltageDomain()
system.cpu_clk_domain = SrcClockDomain(clock = '1GHz',voltage_domain= system.cpu_voltage_domain)
system.membus = SystemXBar()
system.l2bus = L2XBar()
#multiprocess =[Process(cmd = 'tests/test-progs/hello/bin/riscv/linux/a.out', pid = 100 + i) for i in xrange(2)]
multiprocess =[Process(cmd = 'tests/test-progs/hello/src/a.out', pid = 100 + i) for i in xrange(2)]
#cpu config
for i in xrange(2):
system.cpu[i].icache = L1ICache(opts)
system.cpu[i].dcache = L1DCache(opts)
system.cpu[i].icache.connectCPU(system.cpu[i])
system.cpu[i].dcache.connectCPU(system.cpu[i])
system.cpu[i].icache.connectBus(system.l2bus)
system.cpu[i].dcache.connectBus(system.l2bus)
system.cpu[i].createInterruptController()
system.cpu[i].workload = multiprocess[i]
system.cpu[i].createThreads()
system.l2cache = L2Cache()
system.l2cache.cpu_side = system.l2bus.master
system.l2cache.mem_side = system.membus.slave
system.system_port = system.membus.slave
system.mem_ctrl = DDR3_1600_8x8()
system.mem_ctrl.range = system.mem_ranges[0]
system.mem_ctrl.port = system.membus.master
root = Root(full_system = False, system = system)
# instantiate all the objects that we have created above
m5.instantiate()
print("The simulation is going to start in 3 2 1 .. GOOOO! ")
exit_event = m5.simulate()
print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause())) _______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
