Hello Everyone,
I am trying to simulate D-cache with one target per mshr, I tried changing
the parameter "tgts_per_mshr" defined in "configs/common/Caches.py" to 1,
it does not work.
This is because when we allocate target for existing MSHR, we always check
the "tgts_per_mshr" parameter after allocating the second target and
blocks the requests coming from LSQ.
I tried copying the blocking target code to an allocateMissBuffer function
defined and declared in "src/mem/cache/base.hh" as:
*BEFORE*:
MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send =
true)
{
MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
pkt, time, order++,
allocOnFill(pkt->cmd));
if (mshrQueue.isFull()) {
setBlocked((BlockedCause)MSHRQueue_MSHRs);
}
if (sched_send) {
// schedule the send
schedMemSideSendEvent(time);
}
return mshr;
}
*AFTER:*
MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send =
true)
{
MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,
pkt, time, order++,
allocOnFill(pkt->cmd));
if (mshrQueue.isFull()) {
setBlocked((BlockedCause)MSHRQueue_MSHRs);
}
* if (mshr->getNumTargets() == numTarget) {*
* //cout << "Blocked: " << name() << endl;*
* noTargetMSHR = mshr;*
* setBlocked(Blocked_NoTargets);*
* }*
if (sched_send) {
// schedule the send
schedMemSideSendEvent(time);
}
return mshr;
}
I also change the "tgts_per_mshr" defined in "configs/common/Caches.py" to
1.
But simulation goes into an infinite loop and does not end.
Does anyone have the technique to create Blocking caches with 1 target per
MSHR entry?
Best regards,
Abhishek
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