Hi Gabe,
One additional question, regarding another instruction I was trying to
implement (FCMOVNBE).
I thought of emulating a sequence similar what we have for CMOVNBE.
def macroop CMOVNBE_R_R
{
mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, regm, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_M
{
ld t1, seg, sib, disp
mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, t1, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_P
{
rdip t7
ld t1, seg, riprel, disp
mov reg, reg, reg, flags=(CCvZF,)
mov reg, reg, t1, flags=(nCCvZF,)
};
However, I think this implementation is made easier because of the usage of the
mov microop which seems to be a condRegOp. However movfp being a FPUnaryOp, I
assume I can’t translate a similar sequence using movfp for FCMOVNBE. Is there
an alternate microop I can make use of, or should I implement a microop or is
there an alternate workaround?
Thanks,
Shyam
> On Apr 13, 2019, at 6:57 PM, Shyam Murthy <[email protected]> wrote:
>
> Hi Gabe,
>
> Thanks for the help with the FRNDINT instruction.
> I was trying to implement another instruction, namely FISTP. This was my
> initial implementation
> def macroop FISTP {
> cvtf_d2i t1, st(0)
> movfp st(0), t1
> pop87
> };
> But I think the instruction writes to a destination, I was unsure how to
> specify the same. (which I will have to specify in place of highlighted st(0)
> here)
> Is this approach correct for this instruction, because I thought it was
> similar to FRNDINT otherwise, with the addition of extra POP instruction to
> pop st(0)?
>
> Thanks,
> Shyam
>
>
> On Sun, Apr 7, 2019 at 2:23 AM Gabe Black <[email protected]
> <mailto:[email protected]>> wrote:
> Hy Shyam. That microop takes a floating point register as it's source and an
> integer register as its destination. You're passing in two floating point
> indexes which won't work. To avoid implementing a new microop (too many
> microops is probably not realistic), you could use the mov2fp microop to move
> the newly converted value in an integer microcode only register (like t1, for
> instance) back into an FP register like st(0).
>
> Gabe
>
> On Fri, Apr 5, 2019 at 6:53 PM Shyam Murthy <[email protected]
> <mailto:[email protected]>> wrote:
> Hi Gabe,
>
> I wrote this implementation for the frndint macroop:
> def macroop FRNDINT {
> cvtf_d2i st(0), st(0)
> };
>
> However, when I run the application using this instruction on gem5, I seem to
> get this error: gem5.opt: build/X86/cpu/simple_thread.hh:251: RegVal
> SimpleThread::readIntReg(int): Assertion `flatIndex < TheISA::NumIntRegs'
> failed.
> I just wanted to know what I was missing in my implementation for FRNDINT
> macroop?
>
> Thanks,
> Shyam
>
>
> On Sun, Mar 31, 2019 at 4:09 PM Shyam Murthy <[email protected]
> <mailto:[email protected]>> wrote:
> Thanks a lot for the clarification Gabe.
>
> Thanks,
> Shyam
>
> On Sun, Mar 31, 2019 at 6:29 AM Gabe Black <[email protected]
> <mailto:[email protected]>> wrote:
> Hi Shyam. There are float to integer and integer to float conversion microops
> in src/arch/x86/isa/microops/fpop.isa which start with cvt_* which is short
> for convert. You can definitely implement new instructions and submit the
> code for review. There are instructions in the CONTRIBUTING.md file in the
> root of the gem5 source tree.
>
> Gabe
>
> On Fri, Mar 29, 2019 at 4:21 PM Shyam Murthy <[email protected]
> <mailto:[email protected]>> wrote:
> Apologize for the wrong title in my previous email. Correcting.
>
> Thanks,
> Shyam
>
> On Fri, Mar 29, 2019 at 6:16 PM Shyam Murthy <[email protected]
> <mailto:[email protected]>> wrote:
> Hi Gabe,
>
> As I am trying to run SPEC 2017 on gem5 in SE mode, I ran into some
> unimplemented instructions namely frndint, fsqrt and fistp to name a few. I
> see that within the src/arch/x86/isa/insts/x87/arithmetic folder, there are
> placeholder files to write implementations for some of the macro operations,
> like square root and rounding. Can I write my implementations and have my
> code reviewed, so that it can be checked in?
> In addition, for float to integer operation, I did not find any corresponding
> micro-op in the folder src/arch/x86/isa/microops, is there already a
> corresponding micro-op (that I missed), or should I write my own?
>
> Thanks,
> Shyam
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