Thank you for pointing me in the right direction! I think I've got it working now for VIPER and the TCPs. I'll double check that the numbers make sense after a few runs.
Thanks! Devin Lafford On Thu, Apr 18, 2019, 10:40 AM Gutierrez, Anthony <anthony.gutier...@amd.com> wrote: > The stat is 0 because it is declared as part of the base CacheMemory class > in Ruby, however the TCP controller in VIPER does not seem to use the stat. > > > > What is missing is an action in the sm file which updates the cache stats, > and calls to that action from the appropriate transitions. > > > > You can see an example of how the stats can be updated in another sm file, > like MOESI_AMD_Base-CorePair.sm > > > > Tony > > > > *From:* gem5-users <gem5-users-boun...@gem5.org> *On Behalf Of *Devlafford > . > *Sent:* Tuesday, April 16, 2019 3:13 PM > *To:* gem5-users@gem5.org > *Subject:* [gem5-users] AMD APU Cache Hit Statistics > > > > Hello, > > > > I am trying to use AMD’s APU model for gem5 found at > https://gem5.googlesource.com/amd/gem5/+/agutierr/master-gcn3-staging to > perform a sensitivity analysis of cache behavior on various GPU workloads, > but it doesn’t look like cache statistics are being tracked correctly. > Looking in the stats file at system.ruby.tcp_cntrl0.L1cache.demand_accesses > shows that there are zero cache accesses, and the same goes for the other > CUs’ TCPs. Should these statistics be tracked? > > > > I am running the Floyd-Warshall benchmark from the Pannotia Benchmark set > with the 512 vertex and 64k edge graph provided in the dataset, and I > wouldn’t imagine that this entire dataset fits into the register file. Any > ideas for what I’m doing wrong? > > > > I was directed by Matt Sinclair to ask Tony Gutierrez specifically about > this. > > > > Thank you, > > > > Devin Lafford > _______________________________________________ > gem5-users mailing list > gem5-users@gem5.org > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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