Hello everyone, I am PhD student and new with gem5, I have a multicore system with 2 private cache levels (DL1, IL1 and L2) and 1 shared L3/LLC. I am using classic memory system, I know this model is non-inclusive, non-exclusive.
For my research I need to bypass some blocks from L3, I mean when some blocks are read I want to write them to L1 and L2 and not write them in L3, and when some blocks are evicted from L2, if they are dirty, I want to write them to Main Memory and not to L3. Is it possible to bypass some blocks from L3 reading the accesses messages? I think I just need to change cache.cc, is it right? I really apreciate your help, thanks in advance.
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