Has anyone used Model Specific register in caches? That is, to set single bit value in any of the MSR from caches?
Best regards, Abhishek On Wed, May 15, 2019 at 2:54 PM Abhishek Singh < [email protected]> wrote: > Hello Everyone and Gabe, > > I am having difficulty in finding a way to implment a new register in X86 > ISA which is set one when an eviction occurs in dCache. > > Does anyone know which files, I should look into or any suggestions on how > to achieve this implementation? > > > Best regards, > > Abhishek >
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