Hi Eliot, gem5 already implements the AArch32 [1] and AArch64 [2] data cache maintenance instructions by VA. Can you use these, or do you need to add some custom functionality?
[1]: https://github.com/gem5/gem5/commit/eeb36e5b6e81c6b9ea6a0c3c97573e762e58ae05#diff-3d3b3ed6a45c8cdc9d511a13c6caaba6 [2]: https://github.com/gem5/gem5/commit/0c0ccad52595e837301eebcf8597862d9abb4f9c#diff-3d3b3ed6a45c8cdc9d511a13c6caaba6 Nikos On 07/06/2019 02:20, Eliot Moss wrote: > Dear gem5 community -- > > I am doing some work where forcing cache line clean (write-back), > invalidate (without clean), and clean with invalidate, for a > given cache line in virtual address space, in user mode, would > be helpful. At present I have a back door "hack" -- some registers > in a special device, where I write a virtual address and then use > internal simulator action to clean the corresponding line, etc. > > Where in the code base would I look to add the actual instruction > support? Obviously it's a subfunction of mcr (move to control > register), but I could not puzzle out the decoding of all of this > to determine _where_ I need to make a code change ... > > Regards, and thanks in advance -- Eliot Moss > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
