Hi all, I've been trying to measure the impacts of increasing the latency in some functional units but found something odd in MinorCPU based cores. I took as an example the ex5_LITTLE.py model (which is an A7-like core in gem5 repo) and increased the latency of all functional units by 900 cycles (just extrapolating). Then, I simulated the same binary (in System Emulation) using the original and modified processor scripts. The final tick count is exactly the same for both simulations. I have doubled checked the config.ini files and the simulated core latencies are correct. I understand that the MinorCPU models an in-order processor, which should be influenced by the higher latencies. Am I missing something in the MinorCPU concept or maybe in my configurations?
PS: I've repeated the same experiment using a DerivO3CPU and in this case the tick count difference is expressive. Regards, Jeckson Dellagostin Souza PhD Candidate Instituto de Informática Universidade Federal do Rio Grande do Sul
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