The ROM is built into gem5 alongside the other microcode. It's prefaced with "def rom", and is mostly in src/arch/x86/isa/insts/romutil.py with a little bit in src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py for implementing far jumps. There's a little bit of machinery which specializes the microcode assembler for x86's specific ROM setup in src/arch/x86/isa/rom.isa and a little bit in src/arch/x86/isa/microasm.py which makes ROM labels a little easier to get at.
The level of parameterization here is probably overkill since nobody else uses the microcode assembler (although they could), and the use of the ROM in x86 is fairly limited, but it should also be pretty easy to ignore if you just want to look at what the code in the ROM is doing or play around with it a bit, or even extend it for whatever reason. Unlike in many real CPUs, there is no support for loading different microcode or modifying the microcode at run time, whether that's code that implements any particular instruction or that goes into the ROM (which is almost just another big instruction with multiple entry points). Gabe On Tue, Aug 6, 2019 at 3:10 PM Jason Lowe-Power <[email protected]> wrote: > Hey Gabe, > > Where does the data in the microcode ROM come from? Do we load it in gem5, > or it loaded by the kernel during boot? > > Thanks, > Jason > > On Wed, Jul 31, 2019 at 7:07 PM Gabe Black <[email protected]> wrote: > >> It looks like the write to CR4 caused an exception in native_write_cr4, >> and that vectored to the kernel's exception handler which decided to panic. >> The first few microops with low micropcs (the number after the . ) are part >> of the instruction, and the ones with high micropcs are part of the "ROM" >> which is common microcode that is available no matter the instruction and >> is handling the exception vectoring. It looks like since the microop which >> did the bad write didn't commit (it had a Fault associated with it), it >> didn't get printed in the trace. That write is probably of either a >> corrupted value, or of a value that gem5 doesn't support but your system >> (which KVM is delegating to) does. >> >> Gabe >> >> On Tue, Jul 30, 2019 at 7:55 PM Pouya Fotouhi <[email protected]> >> wrote: >> >>> Hi All, >>> >>> I'm having issues booting kernel with Simple Timing CPU. My kernel >>> (4.15) boots fine with using KVM CPU and issue persist with Atomic and O3, >>> so I thought it's possibly gem5 implementation of x86 instructions. >>> >>> Call trace for the Kernel oops I'm getting is the following: >>> identify_cpu+0x4b1/0x580 >>> identify_boot_cpu+0x10/0x75 >>> check_bugs+0x2a/0x7fb >>> ? kmem_cache_alloc+0x19f/0x1b0 >>> ? delayacct_init+0x52/0x70 >>> start_kernel+0x4cc/0x511 >>> x86_64_start_reservations+0x24/0x26 >>> x86_64_start_kernel+0x74/0x77 >>> secondary_startup_64+0xa5/0xb0 >>> >>> RIP and RSP: >>> RIP: native_write_cr4+0x4/0x10 RSP: ffffffff82403e28 >>> >>> Looking at the Exec traces, I have: >>> [...] >>> 357797977250: system.cpu1 A0 T0 : @native_write_cr4+4.32949 : >>> Microcode_ROM : or t6, t5, t6 : IntAlu : D=0x0000000000014100 >>> flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> 357797977500: system.cpu1 A0 T0 : @native_write_cr4+4.32950 : >>> Microcode_ROM : wrflags %cc0, t6b, t10b : IntAlu : D=0x0000000000000028 >>> >>> flags=(IsInteger|IsCC|IsSerializing|IsSerializeAfter|IsNonSpeculative|IsMicroop|IsDelayedCommit) >>> 357797977500: system.cpu0 A0 T0 : @__schedule+298.2 : JNZ_I : wrip >>> , t1, t2 : IntAlu : >>> flags=(IsInteger|IsCC|IsControl|IsCondControl|IsMicroop|IsLastMicroop) >>> 357797977750: system.cpu0 A0 T0 : @__schedule+392 : and >>> DS:[r13], 0xfffffffffffffff7 >>> 357797977750: system.cpu0 A0 T0 : @__schedule+392.0 : >>> AND_LOCKED_M_I.mfence : IntAlu : >>> flags=(IsMemBarrier|IsMicroop|IsDelayedCommit|IsFirstMicroop) >>> 357797977750: system.cpu1 A0 T0 : @native_write_cr4+4.32951 : >>> Microcode_ROM : eret 0 : No_OpClass : flags=(IsMicroop|IsLastMicroop) >>> 357797978000: system.cpu1 A0 T0 : @general_protection : NOP >>> : IntAlu : flags=() >>> >>> I went over the micro ops once, and I couldn't find any issues (given >>> it's my first time looking at micro ops). I was wondering if someone with >>> enough expertise can check and see if there is something I'm missing here. >>> The whole sequence (with tick and cpu_ID omitted): >>> >>> @native_write_cr4 : push rbp >>> @native_write_cr4.1 : PUSH_R : subi rsp, rsp, 0x8 : IntAlu : >>> D=0xffffc90000123ea8 flags=(IsInteger|IsMicroop|IsLastMicroop) >>> @native_write_cr4+1 : mov rbp, rsp >>> @native_write_cr4+1.0 : MOV_R_R : mov rbp, rbp, rsp : IntAlu : >>> D=0xffffc90000123ea8 >>> flags=(IsInteger|IsMicroop|IsLastMicroop|IsFirstMicroop) >>> @native_write_cr4+4.32890 : Microcode_ROM : slli t4, t1, 0x4 : >>> IntAlu : D=0x00000000000000d0 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4 : push rbp >>> @native_write_cr4.1 : PUSH_R : subi rsp, rsp, 0x8 : IntAlu : >>> D=0xffffc90000123ea8 flags=(IsInteger|IsMicroop|IsLastMicroop) >>> @native_write_cr4+1 : mov rbp, rsp >>> @native_write_cr4+1.0 : MOV_R_R : mov rbp, rbp, rsp : IntAlu : >>> D=0xffffc90000123ea8 >>> flags=(IsInteger|IsMicroop|IsLastMicroop|IsFirstMicroop) >>> @native_write_cr4+4.32890 : Microcode_ROM : slli t4, t1, 0x4 : >>> IntAlu : D=0x00000000000000d0 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32891 : Microcode_ROM : ld t2, IDTR:[t4 + 0x8] : >>> MemRead : D=0x00000000ffffffff A=0xfffffe00000000d8 >>> flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32892 : Microcode_ROM : ld t4, IDTR:[t4] : >>> MemRead : D=0x81a08e0000101550 A=0xfffffe00000000d0 >>> flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32893 : Microcode_ROM : chks , t4b, 0x3 : IntAlu >>> : flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32894 : Microcode_ROM : srli t10, t4, 0x10 : >>> IntAlu : D=0x000081a08e000010 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32895 : Microcode_ROM : andi t5, t10, 0xf8 : >>> IntAlu : D=0x0000000000000010 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32896 : Microcode_ROM : andi t0w, t10w, 0x4 : >>> IntAlu : D=0x0000000000000020 >>> flags=(IsInteger|IsCC|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32897 : Microcode_ROM : br 0x8084 : No_OpClass : >>> flags=(IsCC|IsControl|IsCondControl|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32900 : Microcode_ROM : ld t3, TSG:[t5] : >>> MemRead : D=0x00af9b000000ffff A=0xfffffe000002d010 >>> flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32901 : Microcode_ROM : chks , t3, 0x7 : IntAlu >>> : flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32902 : Microcode_ROM : wrdl %ctrl145, t3, t10 : >>> IntAlu : D=0x000000000000abd0 >>> >>> flags=(IsInteger|IsSerializing|IsSerializeAfter|IsNonSpeculative|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32903 : Microcode_ROM : wrdh t9, t4, t2 : IntAlu >>> : D=0xffffffff81a01550 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32904 : Microcode_ROM : rdsel t11b, t11b, >>> %ctrl128 : IntAlu : D=0x0000000000000000 >>> flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32905 : Microcode_ROM : rdattr t10, %ctrl184, : >>> IntAlu : D=0x000000000000abd0 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32906 : Microcode_ROM : andi t10, t10, 0x3 : >>> IntAlu : D=0x0000000000000000 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32907 : Microcode_ROM : rdattr t5, %ctrl179, : >>> IntAlu : D=0x000000000000abd0 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32908 : Microcode_ROM : andi t5, t5, 0x3 : >>> IntAlu : D=0x0000000000000000 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32909 : Microcode_ROM : sub t0, t5, t10 : IntAlu >>> : D=0x0000000000000020 flags=(IsInteger|IsCC|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32910 : Microcode_ROM : mov t11b, t0b, t0b : >>> IntAlu : D=0x0000000000000000 >>> flags=(IsInteger|IsCC|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32911 : Microcode_ROM : srli t12, t4, 0x20 : >>> IntAlu : D=0x0000000081a08e00 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32912 : Microcode_ROM : andi t12, t12, 0x7 : >>> IntAlu : D=0x0000000000000000 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32913 : Microcode_ROM : subi t0, t12, 0x1 : >>> IntAlu : D=0x0000000000000008 >>> flags=(IsInteger|IsCC|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32914 : Microcode_ROM : br 0x8096 : No_OpClass : >>> flags=(IsCC|IsControl|IsCondControl|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32915 : Microcode_ROM : br 0x8098 : No_OpClass : >>> flags=(IsCC|IsControl|IsCondControl|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32916 : Microcode_ROM : mov t6, t6, rsp : IntAlu >>> : D=0xffffc90000123ea8 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32917 : Microcode_ROM : br 0x8099 : No_OpClass : >>> flags=(IsControl|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32921 : Microcode_ROM : andi t6b, t6b, 0xf0 : >>> IntAlu : D=0xffffc90000123ea0 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32922 : Microcode_ROM : subi t6, t6, 0x30 : >>> IntAlu : D=0xffffc90000123e70 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32923 : Microcode_ROM : wrip , t0, t9 : IntAlu : >>> flags=(IsInteger|IsControl|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32924 : Microcode_ROM : srli t5, t4, 0x10 : >>> IntAlu : D=0x000081a08e000010 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32925 : Microcode_ROM : andi t5, t5, 0xff : >>> IntAlu : D=0x0000000000000010 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32926 : Microcode_ROM : wrdl %ctrl140, t3, t5 : >>> IntAlu : D=0x000000000000abd0 >>> >>> flags=(IsInteger|IsSerializing|IsNonSpeculative|IsMicroop|IsDelayedCommit|IsSquashAfter) >>> @native_write_cr4+4.32927 : Microcode_ROM : limm t10, 0 : IntAlu : >>> D=0x0000000000000000 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32928 : Microcode_ROM : rdsel t10w, t10w, >>> %ctrl127 : IntAlu : D=0x0000000000000010 >>> flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32929 : Microcode_ROM : wrsel %ctrl127, t5w, : >>> IntAlu : D=0x0000000000000010 >>> >>> flags=(IsInteger|IsSerializing|IsSerializeAfter|IsNonSpeculative|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32930 : Microcode_ROM : ldst t0, HS:[t6] : >>> MemRead : D=0xffff88801fd0f040 A=0xffffc90000123e70 >>> flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32931 : Microcode_ROM : ldst t0, HS:[t6 + 0x28] >>> : MemRead : D=0xffffc90000123ea8 A=0xffffc90000123e98 >>> flags=(IsInteger|IsMemRef|IsLoad|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32932 : Microcode_ROM : st t15, HS:[t6] : >>> MemWrite : D=0x0000000000000000 A=0xffffc90000123e70 >>> flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32933 : Microcode_ROM : st t7, HS:[t6 + 0x8] : >>> MemWrite : D=0xffffffff8106ca84 A=0xffffc90000123e78 >>> flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32934 : Microcode_ROM : st t10, HS:[t6 + 0x10] : >>> MemWrite : D=0x0000000000000010 A=0xffffc90000123e80 >>> flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32935 : Microcode_ROM : rflags t10, %cc0, %cc1 : >>> IntAlu : D=0x00000000000000ad >>> flags=(IsInteger|IsCC|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32936 : Microcode_ROM : st t10, HS:[t6 + 0x18] : >>> MemWrite : D=0x00000000000000ad A=0xffffc90000123e88 >>> flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32937 : Microcode_ROM : st rsp, HS:[t6 + 0x20] : >>> MemWrite : D=0xffffc90000123ea8 A=0xffffc90000123e90 >>> flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32938 : Microcode_ROM : rdsel t5w, t5w, %ctrl128 >>> : IntAlu : D=0x0000000000000000 >>> flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32939 : Microcode_ROM : st t5, HS:[t6 + 0x28] : >>> MemWrite : D=0x0000000000000000 A=0xffffc90000123e98 >>> flags=(IsInteger|IsMemRef|IsStore|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32940 : Microcode_ROM : mov rsp, rsp, t6 : >>> IntAlu : D=0xffffc90000123e70 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32941 : Microcode_ROM : wrsel %ctrl128, t11w, : >>> IntAlu : D=0x0000000000000000 >>> >>> flags=(IsInteger|IsSerializing|IsSerializeAfter|IsNonSpeculative|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32942 : Microcode_ROM : limm t6, 0x14100 : >>> IntAlu : D=0x0000000000014100 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32943 : Microcode_ROM : or t10, t10, t6 : IntAlu >>> : D=0x00000000000141ad flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32944 : Microcode_ROM : srli t5, t4, 0x28 : >>> IntAlu : D=0x000000000081a08e flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32945 : Microcode_ROM : srli t7, t10, 0x9 : >>> IntAlu : D=0x00000000000000a0 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32946 : Microcode_ROM : xor t5, t7, t5 : IntAlu >>> : D=0x000000000081a02e flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32947 : Microcode_ROM : andi t5, t5, 0x1 : >>> IntAlu : D=0x0000000000000000 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32948 : Microcode_ROM : slli t5, t5, 0x9 : >>> IntAlu : D=0x0000000000000000 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32949 : Microcode_ROM : or t6, t5, t6 : IntAlu : >>> D=0x0000000000014100 flags=(IsInteger|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32950 : Microcode_ROM : wrflags %cc0, t6b, t10b >>> : IntAlu : D=0x0000000000000028 >>> >>> flags=(IsInteger|IsCC|IsSerializing|IsSerializeAfter|IsNonSpeculative|IsMicroop|IsDelayedCommit) >>> @native_write_cr4+4.32951 : Microcode_ROM : eret 0 : No_OpClass : >>> flags=(IsMicroop|IsLastMicroop) >>> >>> Best, >>> -- >>> Pouya Fotouhi >>> PhD Candidate >>> Department of Electrical and Computer Engineering >>> University of California, Davis >>> >> _______________________________________________ >> gem5-users mailing list >> [email protected] >> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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