On 10/17/19 10:02 AM, Javed Osmany wrote: > *From:*Javed Osmany > *Sent:* 16 October 2019 07:15 > *To:* [email protected] > *Cc:* Javed Osmany <[email protected]> > *Subject:* FW: Running Dhrystone on GEM5 > > *From:*Javed Osmany > *Sent:* 15 October 2019 17:54 > *To:* [email protected] <mailto:[email protected]> > *Cc:* Javed Osmany <[email protected] > <mailto:[email protected]>> > *Subject:* Running Dhrystone on GEM5 > > Hello > > I have been running the dhrystone benchmark (ARM V7 architecture) on the > ARM ISA Gem5, using the simple.py configuration script found in > configs/learning_gem5/part1 (modified to point to the dhry32-static binary). > > In simple.py, it states > > system.clk_domain.clock = '1GHz' (== 1000 MHz) > > When the benchmark is run on gem5, it states > > Global Frequency set at 1000000000000 ticks per second (== 1 x 10^12) > > QS: What is the [CPU, system] frequency being used in the simulation? > What MHz figure I should be using the calculate the DMIPS/MHz metric? >
You can't without extra information: gem5 only gives you a cycle count. If you make a good CPU on real hardware, that CPU can run at higher frequencies, and therefore has higher DMIPS/MHz. Only ff your gem5 model has models your real CPU accurately enough, you can then make DMIPS/MHz predictions using the maximum hardware operation frequency by counting cycles. > Best regards > > J.Osmany > > > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
