Hello Please see comments in-line.
Tks JO > -----Original Message----- > From: Ciro Santilli [mailto:[email protected]] > Sent: 04 November 2019 18:07 > To: gem5 users mailing list <[email protected]>; Javed Osmany > <[email protected]> > Subject: Re: [gem5-users] devices.py > > > > On 10/29/19 12:44 PM, Javed Osmany wrote: > > Hello > > > > I am trying to model a simple system using the MinorCPU() model. > > > > In the Arm Research Starter kit documentation they give an example > > (page > > 17) where they make use of devices.L1I, devices.L1D, devices.WalkCache > > and devices.L2 to instantiate the L1I$, L1D$, L2$ cache subsystem. > > > > In my simple system model I wanted to make use of an L2 XBAR bus > > connection to connect the L1 and L2 caches. > > > > I assumed that the L2 XBAR would be defined in devices.py, but could > > not find it. The only references to L2XBAR I could find in devices.py > > are the following: > > > > def addL2(self, clk_domain): > > > > if self._l2_type is None: > > > > return > > > > self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain) > > > > self.l2 = self._l2_type() > > > > for cpu in self.cpus: > > > > cpu.connectAllPorts(self.toL2Bus) > > > > self.toL2Bus.master = self.l2.cpu_side > > > > def addCaches(self, need_caches, last_cache_level): > > > > if not need_caches: > > > > # connect each cluster to the memory hierarchy > > > > for cluster in self._clusters: > > > > cluster.connectMemSide(self.membus) > > > > return > > > > cluster_mem_bus = self.membus > > > > assert last_cache_level >= 1 and last_cache_level <= 3 > > > > for cluster in self._clusters: > > > > cluster.addL1() > > > > if last_cache_level > 1: > > > > for cluster in self._clusters: > > > > cluster.addL2(cluster.clk_domain) > > > > if last_cache_level > 2: > > > > max_clock_cluster = max(self._clusters, > > > > key=lambda c: > > c.clk_domain.clock[0]) > > > > self.l3 = L3(clk_domain=max_clock_cluster.clk_domain) > > > > self.toL3Bus = L2XBar(width=64) > > > > self.toL3Bus.master = self.l3.cpu_side > > > > self.l3.mem_side = self.membus.slave > > > > cluster_mem_bus = self.toL3Bus > > > > Am I correct in thinking that the actual instantiation of the L2XBar > > bus is not done in devices.py? > > > > Do you mean definition of L2XBar, since the instantiation is "self.toL2Bus = > L2XBar(width=64, clk_domain=clk_domain)"? [JO: ] [JO: ] Okay, if this is the instantiation of L2XBAR, but I was not able to connect my L1$ and L2$ to the XBAR. Will revisit, given the information you have provided. > > About the definition, "git grep L2XBar" shows "src/mem/XBar.py:137:class > L2XBar(CoherentXBar):", isn't that the one? [JO: ] [JO: ] Yes, this the definition. The issue I was having was trying to connect to the instantiation of the L2XBAR. > > > Best regards > > > > J.Osmany > > > > > > _______________________________________________ > > gem5-users mailing list > > [email protected] > > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users > > > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, > please notify the sender immediately and do not disclose the contents to any > other person, use it for any purpose, or store or copy the information in any > medium. Thank you. _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
