Hello All, I was wondering if there is a way to specify the bandwidths for the different caches in the simulated system? For example, let's say I want to simulate a system that resembles the Ivy Bridge architecture as much as possible which according to this link ( https://en.wikichip.org/wiki/intel/microarchitectures/ivy_bridge_(client)) has the following: 1- 16B/cycle L1I-cache bandwidth 2- 32B/cycle L1D-cache load bandwidth 3- 16B/cycle L1D-cache store bandwidth 4- 32B/cycle L2-L1 bandwidth
Is there an easy way to configure those values in either the Ruby or classical memory systems? Thanks in advance, Shehab
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