Dear Anuj, I am not sure what you mean by "using bare-metal RISCV ISA support". In case you are referencing to the Diploma Thesis by Robert Scheffel [1], you can find his work in a fork of gem5 [2]. Unfortunately, we never had the time to bring those changes to the mainline gem5. Let me know if you have any problems with setting this up.
I did not follow the development in mainline gem5 and I am not sure what the current status of RISC-V support is there. Maybe what you ask is also already supported there. [1] https://cfaed.tu-dresden.de/publications?pubId=2203 [2] https://github.com/tud-ccc/gem5-riscv-ccc Best, Chrisitan Anuj Falcon <[email protected]> writes: > What is the exact procedure to execute a binary with TimingSimpleCPU using > bare-metal RISCV ISA support ? (Without system call support) > -- > --------------------------------------------------------------------------------- > J ANUJ > --------------------------------------------------------------------------------- > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
