On 12/10/2019 10:51 AM, Armel Jeatsa wrote:
I would like to know if in gem5, a *data* in the *cpu cache* can be accessed by *one and only one* process (the process which has stored this data in the cache). i saw that in the gem5 source code, the class*CacheBlk* has an attribute /*task_id*/ so the response to my question is probably *YES*, but i want to be sure about that.
Assuming we're talking about the MESI protocol for cache consistency (M = modifed, E = exlusive, S = shared, I = invalid), once a line is written (M state) it can be read by another CPU, which would cause the line to go to S state in both caches. So the answer is *no*, if we're talking about the same address space or a shared-memory page. Other protocols might be out there, but I think this is pretty standard. Eliot Moss _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
