[gem5-users] What is the default coherence mechanism in gem5 for multicore systems?

[Francisco Carlos]

Hi all,

I am currently running simulation in a multicore processor. I connect the 
memory system as follow:

for i in range(np):
    system.cpu[i].icache = L1_ICache()
    system.cpu[i].dcache = L1_DCache()
    system.cpu[i].icache.connectCPU(system.cpu[i])
    system.cpu[i].dcache.connectCPU(system.cpu[i])

system.l2cache = L2Cache()
system.l2bus = L2XBar()

#np means number of processor and it is a parameter
for i in range(np):
    system.cpu[i].icache.connectBus(system.l2bus)
    system.cpu[i].dcache.connectBus(system.l2bus)
system.l2cache.connectCPUSideBus(system.l2bus)
system.l2cache.connectMemSideBus(system.membus)

In summary, to each core I have private Icache and Dcache which are connected 
to an L2 shared cache.

So, my question is: how is the coherence guaranteed in the system, since I do 
not provide this information in my configuration file? Is there a default 
coherency used in the gem5? If so, which is it?

Thanks in advance.

----------------------------------------------------------------------------------------------------------------------------------------------
Francisco Carlos Silva Junior
Ph.D student at University of Brasilia


_______________________________________________
gem5-users mailing list
gem5-users@gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users