With that said For x86 O3CPU, the multi program workload simulation is also broken. So basically one can not multi core simulation using x86 O3CPU with and without SMT.
Also, to all developers who push commit to gem5, please do thorough testing as both of this support was working in older commits! On Mon, Feb 10, 2020 at 3:59 PM Kevin Loughlin <kevlo...@umich.edu> wrote: > Hi all, > > I believe there is indeed at least one bug in O3 CPU implementation when > using SMT in SE mode. Namely, the rename mapping for the zero register on > additional threads fails assert(prev_reg->isZeroReg()) in rename() in > /src/cpu/o3/rename_map.cc. This is because the processor logic does not > consider the mapping of the zero register for additional threads. > > There are two ways to solve this. We could (a) change the isZeroReg() > function to reflect that the architectural zero register does not > necessarily need to be directly mapped, or (b) share a direct-mapped zero > register among threads. I've implemented both, and they both successfully > pass the assert. I'll try to push a patch for one soon. > > Unfortunately, SMT in SE mode still fails for x86 despite this change, as > the processor attempts to read an unmapped address later during execution. > Still trying to debug that. I've only been able to get SMT working in SE > mode for ARMv7. I read somewhere that the x86 TLB implementation in gem5 > might have limited support for TLB, but I have yet to confirm this. Any > help/advice is appreciated. > > I second that SMT support in SE mode should be a priority. > > Best, > > Kevin Loughlin >
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