Hello,
I'm currently working on some optimizations regarding registers in x86
with gem5 and there are some things that I don't understand about their
implementation, especially for CC registers (flags register).
The flags seem to be separated in different registers
(CCREG_ZAPS,CCREG_CFOF, CCREG_DF, CCREG_ECF, CCREG_EZF in
src/arch/x86/regs/ccr.hh).
However, according to the Intel documentation
(https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdfpage
79) all the different flags refer to different bits in a single
flags-register (one bit of the register per flag). My first question is
why in the gem5-x86 implementation the flags (or bits) are mapped to
different registers?
Moreover, some micro-ops count CC registers as source operands. For
example, the macroop INC_R
(src/arch/x86/isa/insts/general_purpose/arithmetic/increment_and_decrement.py,
page 1062 of the Intel documentation) may only set OF, SF, ZF, AF and PF
flags but is not affected by any flag (no source flag!). By looking at
the micro-ops of INC_R, we can see that there is only an "addi" that
configures the flags. Apparently, though, its CC registers can be
*counted* as source registers if the instruction (namely addi) is going
to set at least one of the flags but not all, for what I understand (C++
class AddFlagsImm in build/X86/arch/x86/generated/decoder-ns.cc.inc).
For the micro-op generated by INC_R, OF is used but not CF, which cause
one CC register to be counted as *a source and destination* instead of
just destination, which deviates (arguably) a lot from the Intel
documentation. Does the "_numSrcRegs" member of a StaticInst represent
the number of source registers of this micro-op of this instruction
according to the official documentation or is it just a gem5
implementation trick?
Also, about the ext member of
RegObBase(src/arch/x86/insts/microregop.hh), is it for conditional code
(used in checkCondtion() in src/arch/x86/insts/microop.cc) or for the
flags a micro-op can set, or even both? Because the ext member seems to
be set for CondFlagBit(src/arch/x86/regs/misc.hh), which seems to
represent the flags that are set by a micro-op, or
ConditionTest(scr/arch/x86/insts/microop.hh), which seems to represent
the flags that must be tested by checkCondition(), depending on the
situation. I would like to use this member to know what are the source
flags that are used by a micro-op.
Thanks,
--
Anis Peysieux
Doctorant - Équipe PACAP
Centre de recherche INRIA Rennes - Bretagne Atlantique
Bâtiment 12E, Bureau E301, Campus de Beaulieu,
35042 Rennes Cedex, France
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