Dear All, I wonder how to change the mshr entry number? I use X86 O3 detailed CPU model. I edited the Caches.py, and set the L2 cache mshrs to 20.
class L2Cache(Cache): assoc = 8 tag_latency = 12 data_latency = 12 response_latency = 12 mshrs = 20 tgts_per_mshr = 12 write_buffers = 8 When I look at config.ini: [system.l2] mshrs=20 It looks like the mshrs of L2 has been changed correctly. However, I printed the size of L2 mshr queue in cache.cc, the maximum number is only 10. (I found that isfull function uses the parameter "allocated" to determine the queue is full or not, so I also utilized "allocated" parameter to see the size of mshr queue) So I want to know have I successfully modified the number of mshr? Is my test method right? If all I do is right, it should be a matter of application. Any ideas or suggestions would be helpful. Thank you very much. Rosen
_______________________________________________ gem5-users mailing list firstname.lastname@example.org http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users