Hi, In my stat.txt file, I see that the miss latency given in cycles is almost 15 times greater than the total execution cycles of my gem5 run.
system.switch_cpus.numCycles 31316822936 # number of cpu cycles simulated system.l2.demand_miss_latency::switch_cpus.dtb.walker 476626107789 # number of demand (read+write) miss cycles These results are from simulating with TimingSimpleCPU. However, O3 CPU also gives similar results. Can someone please explain why the miss latencies are larger than the number of execution cycles? Thanks in advance, Regards Sethu
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