Thanks ! On Sun, Mar 15, 2020 at 6:48 PM Kevin Dong <[email protected]> wrote:
> Hi everyone, > > I've solved this problem, and this is a note for the future readers: > > Instead of directly calling queueMemoryWrite() within the L1 controller, > though the type of its parent class, AbstractController, is as same as that > of the directory controller. I found that it may be easier to implement by > creating a new class inherited from the class AbstractController, and > attach it to the L1 controller in the file MESI_Two_Level.py. Besides, its > memory port has to connect to the crossbar port in the file Ruby.py. > > Regards, > Kevin Dong Nai Jia > > > On Sun, Mar 15, 2020 at 2:59 PM Kevin Dong <[email protected]> wrote: > >> Hi everyone, >> >> I am using Ruby cache with the MESI 2-level protocol. I found that only >> the directory controller can call queueMemoryWrite() to send memory write >> requests into the memory controller, but not the L1 caches directly. Should >> I add some extra interconnections for Ruby to connect between L1 caches and >> memory controller? Appreciate any help. Thanks! >> >> Regards, >> Kevin Dong >> > _______________________________________________ > gem5-users mailing list > [email protected] > http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
_______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
