Hi all, >From my understanding,* master simObjects (CPUs, GPUs) generate requests *to the slave simObjects(L1private split cache, membus, L2 cache etc.), slaves responses to the requests.
I want to see both *requests* and *response* packets. I have attached a communication monitor in addPrivateSplitL1Caches function of BaseCPU.py which I believe captures packets only in one direction: CPU to L1_data_cache . ... #----------------Communication Monitor between l1d cache and the CPU #self.dcache_port = dc.cpu_side self.monitor = CommMonitor() self.monitor.trace = MemTraceProbe(trace_file='CPU'+str(self)+'.trc') self.dcache_port = self.monitor.slave self.monitor.master = dc.cpu_side .... My first question is how to get the response packets? Like the response packets from the L1_data_cache to CPU. My second query is, tell me if I am wrong: I need following information from a packet: 1 . sender of the packet 2. receiver of the packet 3. command of the packet 4. physical memory address(if any) In the decoded packets I find packet id (which I assume refers to master/sender (1)), the place where I place the commMonitor() tells me who is the receiver of the packet(2), and decoding the packet gets me (3) and (4). Please correct me if I am doing/assuming anything wrong here. Please see the config.dot.svg to see the system I am simulating. My 3rd query is: the communication monitor I attached has been attached between cache(L1) and the CPU? Thanks for reading my long email. Any help will be highly appreciated. Regards, *Rubel Ahmed*
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