Hello,
I believe what might be missing is a call to perform the writebacks (doWritebacks(wb_pkts, clockEdge(lat+forwardLatency))) before any other cache operations (e.g., access()). This will make sure that the coherence is kept, and you will not mistakenly use stale data. Regards, Daniel Em quarta-feira, 15 de abril de 2020 19:13:16 GMT+2, 周泰宇 <[email protected]> escreveu: I don’t know why the format so garbled. So I post my code again. BaseCache::recvTimingReq(pkt){ wb_pkts.clear(); dirty_blk_count = my_memWriteback(wb_pkts); bool satisfied = false; { PacketList writebacks; satisfied = access(pkt, blk, lat, writebacks); ..... } int BaseCache::my_memWriteback(PacketList &wb_pkts) { int count = 0; tags->forEachBlk([this,&count,&wb_pkts](CacheBlk &blk) mutable{ if(blk.isDirty()){ if(blk.isValid()){ count++; } } my_writebackVisitor(blk,wb_pkts); }); //printf("NmemWriteback count:%d\n",count); return count; } BaseCache::my_writebackVisitor(CacheBlk &blk,PacketList &writebacks) { if (blk.isDirty()) { assert(blk.isValid()); RequestPtr request = std::make_shared( regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId); request->taskId(blk.task_id); if (blk.isSecure()) { request->setFlags(Request::SECURE); } PacketPtr packet = new Packet(request, MemCmd::WriteReq); packet->allocate(); std::memcpy(packet->getPtr, blk.data, blkSize); // packet->dataStatic(blk.data); writebacks.push_back(packet); blk.status &= ~BlkDirty; } } _______________________________________________ gem5-users mailing list [email protected] http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
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