On 4/15/2020 1:13 PM, 周泰宇 wrote:
I don’t know why the format so garbled. So I post my code again.
|BaseCache::recvTimingReq(pkt){ wb_pkts.clear(); dirty_blk_count = my_memWriteback(wb_pkts); bool
satisfied = false; { PacketList writebacks; satisfied = access(pkt, blk, lat, writebacks); ..... }
int BaseCache::my_memWriteback(PacketList &wb_pkts) { int count = 0;
tags->forEachBlk([this,&count,&wb_pkts](CacheBlk &blk) mutable{ if(blk.isDirty()){
if(blk.isValid()){ count++; } } my_writebackVisitor(blk,wb_pkts); }); //printf("NmemWriteback
count:%d\n",count); return count; } BaseCache::my_writebackVisitor(CacheBlk &blk,PacketList
&writebacks) { if (blk.isDirty()) { assert(blk.isValid()); RequestPtr request = std::make_shared(
regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId); request->taskId(blk.task_id); if
(blk.isSecure()) { request->setFlags(Request::SECURE); } PacketPtr packet = new Packet(request,
MemCmd::WriteReq); packet->allocate(); std::memcpy(packet->getPtr, blk.data, blkSize); //
packet->dataStatic(blk.data); writebacks.push_back(packet); blk.status &= ~BlkDirty; } }|
Silly email tool wrecked the formatting!
I just wanted to say, good for you in including that last line. I implemented
something like this (in an older version, etc., so I don't think it useful to
share the code here) and forgot that line. It led to a nasty, rarely expressed,
bug, where the line got written back to memory again later, zapping stuff that
had been written by another processor. (The setup was one with intentionally
non-(hardware)-coherent caches, and this broke the software managed coherence.)
Best wishes - EM
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