An update, regarding the tests I performed. I used to run the following command:
./build/X86/gem5.opt -d out_dir --stats-file=stats.stat configs/example/fs.py --checkpoint-dir=cpt_dir/spec2006 --checkpoint-restore=5 --caches --l2cache --maxinsts=7000000 --warmup-insts=1000000 --standard-switch=1000000 kernel=kernel_dir/x86_64-vmlinux-2.6.22.9 --disk-image=disk_dir/ubuntu-14.04.img ;
I also tried the --restore-with-cpu options with TimingSimpleCPU/DerivO3CPU/NonCachingSimpleCPU but the issue persist. Moreover I tried to run the simulation without warmup otpion, again the assertion was triggered.
The only case, where the simulation completed succesfully was with the TraceCPU option. Simulation over elastic traces. ./build/X86/gem5.opt -d my_out --stats-file=stats.stat configs/example/etrace_replay.py --cpu-type=TraceCPU --caches --l2cache --inst-trace-file=$el_tr_dir/system.switch_cpus.traceListener.fetchtrace.proto.gz --data-trace-file=$el_tr_dir/system.switch_cpus.traceListener.deptrace.proto.gz;
Note that the assertion triggered only in some benchmarks from SPEC2006 suite, and only in dcache test scenario.
Is there any idea how can I overpass the issue on full system emulation? Cheers, Michail Στις 2020-06-22 20:41, Michail Mavropoulos via gem5-users έγραψε:
Hello all, I am facing an assertion when I try to flush the dcache periodically, using a sheduling timing event. I have set up a recurring timing event, and on the handler of this event I try to flush the dcache or icache. For the icache scenario I just call the base.cc::memInvalidate(), see https://gem5.googlesource.com/public/gem5/+/96fce476785a834f102ae69a895e661cf08e47cd/src/mem/cache/base.cc#1585, while for dcache case first I call the writeback (see: https://gem5.googlesource.com/public/gem5/+/96fce476785a834f102ae69a895e661cf08e47cd/src/mem/cache/base.cc#1579) and then the cache invalidation. I have observed that for the dcache scenario the following assertion get triggered, see https://gem5.googlesource.com/public/gem5/+/96fce476785a834f102ae69a895e661cf08e47cd/src/mem/cache/base.cc#1322. Am I doing something wrong during the dl1 cache flushing procedure? Kind regards, Michail _______________________________________________ gem5-users mailing list -- [email protected] To unsubscribe send an email to [email protected] %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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