Hi all,
I am trying to bring in another block into the cache in addition to the
requested block whenever there is a miss. I have written the following the code
in the recvTimingReq() in the miss handling part.
PacketPtr NewPacket = nullptr;// Creating a new packet
RequestPtr req = new Request( pkt->req->getPaddr() + 2*blkSize,
pkt->req->getSize(),
pkt->req->getFlags(),
pkt->req->masterId());// Copying the parameters from the original packet
NewPacket = new Packet(req, pkt->cmd);
NewPacket->allocate();
NewPacket->setPacketType(1);
recvTimingReq(NewPacket);// call to recvTimingReq with the new packet
Note that I have changed the address requested by incrementing it by 2 times
the blockSize.
I have added a bool variable packet_type to distinguish between normal
packet(0) and the additional packet that we are creating(1). We set this
variable in the new packet and we will call the recvTimingReq with this new
packet. I have also made sure that calls will not go into infinite recursion.
In recvTimingResp, to avoid this packet going to CPU we will check if this
packet is a regular one or the one that we created using the bool variable
packet_type. If the packet is a created one we will delete the packet, just
like we delete the prefetch request packets.
Error: But one of the assertions is failed.
<bad format>gem5.opt: build/X86/cpu/simple/timing.cc:823: void
TimingSimpleCPU::completeDataAccess(PacketPtr): Assertion
`_status == DcacheWaitResponse || _status == DTBWaitResponse ||
pkt->req->getFlags().isSet(Request::NO_ACCESS)' failed. Assertion is failed in
completeDataAccess() method as you can see.
I am new to gem5 and I am not sure about the reason behind the assertion fail.
Also, I don't know the reason behind the <bad format> tag in the debug flag
outputs. Is calling the recvTimingReq with a new packet a good idea for
bringing another block? Any other ideas to bring in another block into the
cache are welcome. Any comments are also welcome.
Thanks for your time.
Saideepak.
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