On 7/1/2020 10:53 PM, Saideepak Bejawada via gem5-users wrote:
Thanks. I will try that. How can I add data TLB to the cache? Is it possible
using CacheConfig.py?
Add? Presumably a data TLB already exists. Do you meanL "How do I access the data TLB?" If so,
then the sort of thing that works in my code is:
SimObject *obj = SimObject::find("system.cpu.dstage2_mmu.stage2_tlb");
ArmISA::TLB *tlb = (ArmISA::TLB *)(obj);
The specific type may vary of course, as well as the specific name of the
component, but the
name you can see in your config.ini file output by a simulation run, and it
should not be
too hard to discover the type.\ (e.g., X86ISA::TLB). These will have page
walker classes
associated with them.
Anyway, as you initialize your module you can find and use these connections.
Not as
general perhaps as doing stuff in your .py files, but maybe easier?
Best wishes - EM
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