Hi Jason, Is there a parameter that I can see where my caches are accepting more than one request per cycle or not. Also assuming that I am not sending requests in the same cycle but in different cycles, they still wait for one response to come back before another one is issued. Also after changing my bars and not using the non-coherent ones, i get the same results.
My system is configured as follows: https://drive.google.com/drive/folders/18OtZhS8nEAtlg-BJ7GtoDe_kR_DtxLdd?usp=sharing. Would you be kind enough to check what I am doing wrong?. Your help is much appreciated Thanks, Aamir On Mon, 17 Aug 2020 at 18:38, Jason Lowe-Power <ja...@lowepower.com> wrote: > Hello, > > This depends on your memory system. If your cache can accept more than one > request per cycle, then the CPU can send more than one request. The > `sendTimingReq` returns false when the receiver cannot receive another > request. > > It's hard to know exactly what your memory system looks like, but if > you're using non-coherent crossbars between different levels of caches, > you're probably going to be seeing some errors in your memory. The > non-coherent crossbar was designed to be put below (closer to memory) a > "point-of-coherence" crossbar. Also, I believe that by default that > crossbar is on 16 bytes wide, so a single cache line request could take 4 > cycles, which might be why the CPU is blocking? > > Cheers, > Jason > > On Sun, Aug 16, 2020 at 12:01 PM Muhammad Aamir via gem5-users < > gem5-users@gem5.org> wrote: > >> Hi everyone, >> >> Is it possible to send more than one memory request from the >> dcacheport to the memory system without stalling the pipeline. What i have >> seen so far is that when one memory instruction is send to the memory, then >> another memory request cannot be send to the memory as sendTimingReq >> returns boolean type false. And it has to wait until the previous memory >> response is back then issue the next one . >> >> My goal is to allow the MinorCPU to have overlapping memory requests to >> the memory, therefore is it possible to achieve this by sending more than >> one memory request to the memory? as I cannot figure this out. >> I am currently using noncoherent Xbars to connect my caches and the >> memory system, would I need to change it or is there something else that i >> have to do? >> >> Any help would be appreciated. >> >> Thanks. >> _______________________________________________ >> gem5-users mailing list -- gem5-users@gem5.org >> To unsubscribe send an email to gem5-users-le...@gem5.org >> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s > >
_______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
