I'm not sure about the cache hierarchy issue.

But about Ruby support, I don't think there's any known ARM specific problem, 
and ARM contributors have been specifically pushing Ruby recently, see e.g. see 
Tiago's CHI announcement: https://www.gem5.org/2020/05/29/flexible-cache.html
________________________________
From: chenboya via gem5-users <gem5-users@gem5.org>
Sent: Friday, August 21, 2020 10:50 AM
To: gem5-users@gem5.org <gem5-users@gem5.org>
Cc: chenboya <chenb...@huawei.com>
Subject: [gem5-users] [ARM system] Question about the cleassic cache system


Hi, ALL

I'm doing some design space exploration work using GEM5.
My work is exploring the different cache structures, using ARM cores, classic 
cache structure, and use parsec-3.0 to simulate the multi-core performance.
My system has 4-level caches, every level using L2XBar to connect. Use big 
little clusters, every cluster has the L2 cache shared by cores in the cluster.

Now I meet some problems in the cache structure as below:

1. If I connect all the clusters to one L3 cache then connect to one L4 cache, 
then the full system run is OK.

2. If I connect big clusters directly to L4 cache, other clusters connect to 
one L3 cache then connect to L4 cache, will see the error below (in 
system.terminal):

/home/root/parsec-3.0
 [    0.831546] Unable to handle kernel paging request at virtual address 
aaecd674a901
 [    0.831563] Unable to handle kernel paging request at virtual address 
aaecde551e41
 [    0.831573] Unable to handle kernel paging request at virtual address 
aaecde527e41

3. If I connect big clusters to one L3, other clusters to another L3, and these 
two L3 caches connect to L4 cache, will have SAME error.

If change all cores to Atomic CPU, will not have the page fault error.

All the 3 experiments use same image (the aarch64-ubuntu-trusty-headless.img 
add parsec), and use automatically generated dtb file.
When instantiation, the 3 structures can be generated successfully.

So are there any limits about classic mode memory system for ARM? For example, 
cannot support more than one L3 caches or asymmetry hierarchies?
Should I using Ruby to replace it?

In Andreas Hansson's 2015 slides, he said Ruby has some compatibility problems 
for ARM.
FSConfig.py also warns that Ruby on ARM is not working properly yet. Has those 
problems solved now?


-----Original Message-----
From: gem5-users-requ...@gem5.org [mailto:gem5-users-requ...@gem5.org]
Sent: 2020年8月21日 8:23
To: gem5-users@gem5.org
Subject: gem5-users Digest, Vol 169, Issue 52

Send gem5-users mailing list submissions to
        gem5-users@gem5.org

To subscribe or unsubscribe via email, send a message with subject or body 
'help' to
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When replying, please edit your Subject line so it is more specific than "Re: 
Contents of gem5-users digest..."

Today's Topics:

   1. Re: KVM does not work  (chenboya)
   2. Re: Functional read failed while using pthread lock in program
      (Jason Lowe-Power)
   3. Packet request send directly to memory without searching in cache
      (Muhammad Aamir)
   4. issues in FS mode with TimingSimpleCPU+Multicore (JASPINDER KAUR)


----------------------------------------------------------------------

Date: Thu, 20 Aug 2020 14:55:05 +0000
From: chenboya <chenb...@huawei.com>
Subject: [gem5-users] Re: KVM does not work
To: "gem5-users@gem5.org" <gem5-users@gem5.org>
Message-ID: <ae460ec2e47d40f99f783efc7e42d...@huawei.com>
Content-Type: text/plain; charset="utf-8"

There are some GIC issues about running the KVM mode, fortunately an engineer 
had given the solution.
Here are some discussions about the KVM mode for ARM.

https://gem5.atlassian.net/browse/GEM5-547


-----Original Message-----
From: gem5-users-requ...@gem5.org [mailto:gem5-users-requ...@gem5.org]
Sent: 2020年8月12日 9:46
To: gem5-users@gem5.org
Subject: gem5-users Digest, Vol 169, Issue 31

Send gem5-users mailing list submissions to
        gem5-users@gem5.org

To subscribe or unsubscribe via email, send a message with subject or body 
'help' to
        gem5-users-requ...@gem5.org

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When replying, please edit your Subject line so it is more specific than "Re: 
Contents of gem5-users digest..."

Today's Topics:

   1. KVM does not work (毛允飞)
   2. Re: KVM does not work (Giacomo Travaglini)


----------------------------------------------------------------------

Date: Wed, 12 Aug 2020 16:40:48 +0800
From: 毛允飞 <fgzs...@gmail.com>
Subject: [gem5-users] KVM does not work
To: gem5-users@gem5.org
Message-ID:
        <cadszstvhevwigr3p5rvunzkrpjakhvaiow89b6snxjn7dup...@mail.gmail.com>
Content-Type: multipart/alternative;
        boundary="000000000000c0216705acaa2553"

--000000000000c0216705acaa2553
Content-Type: text/plain; charset="UTF-8"

Hi All
I run the fs_bigLITTLE.py script in gem5, but there is no information in the 
m5term console. I don't know what went wrong,

INFO:
Global frequency set at 1000000000000 ticks per second
info: Simulated platform: VExpress_GEM5_V1
info: kernel located at:
/home/tracy/gem5/fs_image_arm/binaries/vmlinux.vexpress_gem5_v1_64.20170616
warn: Highest ARM exception-level set to AArch32 but the workload is for 
AArch64. Assuming you wanted these to match.
system.vncserver: Listening for connections on port 5900
system.terminal: Listening for connections on port 3456
system.realview.uart1.device: Listening for connections on port 3457
system.realview.uart2.device: Listening for connections on port 3458
system.realview.uart3.device: Listening for connections on port 3459
0: system.remote_gdb: listening for remote gdb on port 7000
warn: CoherentXBar system.membus has no snooping ports attached!
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080000
info: Loading DTB file: m5out/system.dtb at address 0x88000000
info: KVM: Coalesced MMIO disabled by config.
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue @ 0.  Starting simulation...
warn: Returning zero for read from miscreg pmintenset_el1
warn: Returning zero for read from miscreg pmintenclr_el1
warn: Returning zero for read from miscreg pmcr_el0
warn: Returning zero for read from miscreg pmcntenset_el0
warn: Returning zero for read from miscreg pmcntenclr_el0
warn: Returning zero for read from miscreg pmovsclr_el0
warn: Returning zero for read from miscreg pmswinc_el0
warn: Returning zero for read from miscreg pmselr_el0
warn: Returning zero for read from miscreg pmccntr_el0
warn: Returning zero for read from miscreg pmuserenr_el0
warn: Returning zero for read from miscreg pmovsset_el0
warn: Returning zero for read from miscreg pmevcntr0_el0
warn: Returning zero for read from miscreg pmevcntr1_el0
warn: Returning zero for read from miscreg pmevcntr2_el0
warn: Returning zero for read from miscreg pmevcntr3_el0
warn: Returning zero for read from miscreg pmevcntr4_el0
warn: Returning zero for read from miscreg pmevcntr5_el0
warn: Returning zero for read from miscreg pmevtyper0_el0
warn: Returning zero for read from miscreg pmevtyper1_el0
warn: Returning zero for read from miscreg pmevtyper2_el0
warn: Returning zero for read from miscreg pmevtyper3_el0
warn: Returning zero for read from miscreg pmevtyper4_el0
warn: Returning zero for read from miscreg pmevtyper5_el0
warn: Returning zero for read from miscreg pmccfiltr_el0
warn: SCReg: Access to unknown device dcc0:site0:pos0:fn7:dev0
37507561455500: system.terminal: attach terminal 0



command line: ./build/ARM/gem5.opt configs/example/arm/fs_bigLITTLE.py
--cpu-type=kvm
--kernel=/home/tracy/gem5/fs_image_arm/binaries/vmlinux.vexpress_gem5_v1_64.20170616
--disk=/home/tracy/gem5/fs_image_arm/disks/linaro-minimal-aarch64.img
--big-cpus=1 --little-cpus=0 --caches --mem-size=4GB


Host CPU Achitecture: ARMV8

Host OS: ubuntu 18.04.4



------------------------------

Date: Thu, 20 Aug 2020 09:47:37 -0700
From: Jason Lowe-Power <ja...@lowepower.com>
Subject: [gem5-users] Re: Functional read failed while using pthread
        lock in program
To: gem5 users mailing list <gem5-users@gem5.org>
Cc: VIPIN PATEL <patelvipi...@gmail.com>
Message-ID:
        <CAFEhpUcq4UDF+6pLNsGv9X3iOa=ptvbdjw9ec7rkpl5syxc...@mail.gmail.com>
Content-Type: multipart/alternative;
        boundary="000000000000e66ea205ad51e24d"

--000000000000e66ea205ad51e24d
Content-Type: text/plain; charset="UTF-8"

Hello,

m5threads is not supported in gem5. I would suggest using full system 
simulation if you are investigating multithreaded workloads.

Cheers,
Jason

On Wed, Aug 19, 2020 at 11:42 PM VIPIN PATEL via gem5-users < 
gem5-users@gem5.org> wrote:

> Hi All,
>
> After following the discussion on the JIRA issue for functional read
> failure (https://gem5.atlassian.net/browse/GEM5-676).
> I require pointers on how to use m5threads in Gem5 for execution of
> multithreaded programs?
>
> Thanks in advance.
>
> Regards,
> Vipin Patel
>
> On Tue, Aug 18, 2020 at 11:01 PM VIPIN PATEL <patelvipi...@gmail.com>
> wrote:
>
>> Hi All,
>>
>> I using the GEM5 simulator to collect statistics of a micro-benchmark
>> program. I am encountering the functional read access failed for
>> address "0xXXXX".
>>
>> I have attached the source file of the micro-benchmark program. The
>> simulation is running fine for the case "1" and "4" in the switch
>> construct. The error is encountered for the cases "2" and "3" while I
>> am using pthread locks.
>>
>> I am using the MESI_Two_Level protocol with 4 core configuration(
>> private L1I and L1D cache for each core and shared L2 cache) in SE mode.
>>
>> I have read the discussion on google group "
>> https://groups.google.com/u/1/g/gem5-gpu-dev/c/Wt43jSYYXag";
>> and can infer the issue is generated when we have multiple copies of
>> a block in our system (might be in the transient state) and we tried
>> to perform a store or load to it.
>>
>> Can you point out the way to fix this?
>> Is pthread lock not supported in the gem5? Does the current release
>> of
>> gem5 provide a workaround for this?
>>
>> Any help would be highly appreciated. Thanks in advance.
>>
>> Regards,
>> Vipin
>> Research Scholar
>> IIT Kanpur
>>
> _______________________________________________
> gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an
> email to gem5-users-le...@gem5.org
> %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s

--000000000000e66ea205ad51e24d
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr">Hello,<div><br></div><div>m5threads is not supported in ge= 
m5. I would suggest using full system simulation if you are investigating m= 
ultithreaded workloads.</div><div><br></div><div>Cheers,</div><div>Jason</d=
iv></div><br><div class=3D"gmail_quote"><div dir=3D"ltr"
iv>class=3D"gmail_att=
r">On Wed, Aug 19, 2020 at 11:42 PM VIPIN PATEL via gem5-users &lt;<a href= 
=3D"mailto:gem5-users@gem5.org";>gem5-users@gem5.org</a>&gt; wrote:<br></div=
><blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px
>0.8ex;border=
-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir=3D"ltr">Hi=C2= 
=A0All,<br><div><br></div><div>After following=C2=A0the discussion on the J= 
IRA issue for functional read failure (<a href=3D"https://gem5.atlassian.ne=
t/browse/GEM5-676" target=3D"_blank">https://gem5.atlassian.net/browse/GEM5=
-676</a>).</div><div>I require pointers on how to use m5threads in Gem5 for=  
execution of multithreaded programs?</div><div><br></div><div>Thanks in ad= 
vance.</div><div><br></div><div>Regards,</div><div>Vipin Patel=C2=A0=C2=A0<= 
/div></div><br><div class=3D"gmail_quote"><div dir=3D"ltr" class=3D"gmail_a= 
ttr">On Tue, Aug 18, 2020 at 11:01 PM VIPIN PATEL &lt;<a href=3D"mailto:pat= 
elvipi...@gmail.com" target=3D"_blank">patelvipi...@gmail.com</a>&gt; wrote= 
:<br></div><blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.= 
8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir=3D"lt= 
r">Hi=C2=A0All,<br><div><br></div><div>I using the GEM5 simulator to collec= t 
statistics of a micro-benchmark=C2=A0program. I am encountering the funct= 
ional read access failed for address &quot;0xXXXX&quot;.=C2=A0</div><div><b=
r></div><div>I have attached the source file of the micro-benchmark
r>program=
. The simulation is running fine for the case &quot;1&quot; and &quot;4&quo= t; 
in the switch construct. The error is encountered for the cases &quot;2&= quot; 
and &quot;3&quot; while I am using pthread locks.=C2=A0</div><div><br=
></div><div>I am using the MESI_Two_Level protocol with 4 core
>configuratio=
n( private L1I and L1D cache for each core and shared L2 cache) in SE mode.= 
</div><div><br></div><div>I have read the discussion on google group &quot;= <a 
href=3D"https://groups.google.com/u/1/g/gem5-gpu-dev/c/Wt43jSYYXag"; targ= 
et=3D"_blank">https://groups.google.com/u/1/g/gem5-gpu-dev/c/Wt43jSYYXag</a=
>&quot;</div><div>and can infer the issue is generated when we have
>multipl=
e copies of a block in our system (might be in the transient state) and we = 
tried to perform a store or load to it.</div><div><br></div><div>Can you po= 
int out the way to fix=C2=A0this?=C2=A0</div><div>Is pthread lock not suppo= 
rted in the gem5? Does the current release of gem5 provide a workaround for=  
this?</div><div><br></div><div>Any help would be highly appreciated. Thank= s 
in advance.</div><div><br></div><div>Regards,</div><div>Vipin</div><div>R=
esearch Scholar</div><div>IIT Kanpur</div></div> </blockquote></div> 
_______________________________________________<br>
gem5-users mailing list -- <a href=3D"mailto:gem5-users@gem5.org"; target=3D= 
"_blank">gem5-users@gem5.org</a><br>
To unsubscribe send an email to <a href=3D"mailto:gem5-users-le...@gem5.org=
" target=3D"_blank">gem5-users-le...@gem5.org</a><br>
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s</blockquote></div>

--000000000000e66ea205ad51e24d--

------------------------------

Date: Thu, 20 Aug 2020 22:55:16 +0300
From: Muhammad Aamir <aamir.sa...@bilkent.edu.tr>
Subject: [gem5-users] Packet request send directly to memory without
        searching in cache
To: gem5 users mailing list <gem5-users@gem5.org>
Message-ID:
        <caohrdan3dh6iln7h+tpdwrgsgsdo4hvuof9_j88aia3xnbx...@mail.gmail.com>
Content-Type: multipart/alternative;
        boundary="0000000000004f401305ad5481a3"

--0000000000004f401305ad5481a3
Content-Type: text/plain; charset="UTF-8"

Hi everyone,

As the title suggests, is it possible to send for a request from the CPU asking 
for data in the memory without looking into the caches? If yes, how can it be 
done.

Also is it advisable to create another port like the dcacheport, and connect 
that port directly to the memory bus? i.e. the cpu will have 2 dataports and 
inst port


Any suggestions or comments would be appreciated.

Thanks,
Aamir

--0000000000004f401305ad5481a3
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

<div dir=3D"ltr">Hi everyone,<br><div><br></div><div>As the title suggests,=  
is it possible to send for a request from the CPU asking for data in the m= 
emory without looking into the caches? If yes, how can it be done.</div><di=
v><br></div><div>Also is it advisable to create another port like the
v>dcach=
eport, and connect that port directly to the memory bus? i.e. the cpu will = 
have 2 dataports and inst port</div><div><br></div><div><br></div><div>Any = 
suggestions or comments would=C2=A0be appreciated.<br><br>Thanks,<br>Aamir<=
/div></div>

--0000000000004f401305ad5481a3--

------------------------------

Date: Fri, 21 Aug 2020 12:52:56 +0530
From: JASPINDER KAUR <2017csz0...@iitrpr.ac.in>
Subject: [gem5-users] issues in FS mode with TimingSimpleCPU+Multicore
To: gem5-users@gem5.org
Message-ID:
        <cams_bse+jqmtfdefbj56mejhjzg_aijtpvqdky3k3bk1bwt...@mail.gmail.com>
Content-Type: multipart/alternative;
        boundary="000000000000c32c3b05ad5e1b5c"

--000000000000c32c3b05ad5e1b5c
Content-Type: text/plain; charset="UTF-8"

Dear All,
  I am trying to boot gem5 in FS mode for multiple cores. However, I am facing 
a problem as mentioned below:

   1. Atomic CPU - working properly.
   2. TimingSimpleCPU - Single core - working properly.
   3. TimingSimpleCPU - multiple cores (2 or 4) - the execution stuck after
   partial booting.

*Please let me know where I am doing the mistake. The commans I am using
is:*

>build/X86/gem5.fast configs/example/fs.py --cpu-type=TimingSimpleCPU
--script=/home/user1/simulators/gem5/FS/runs.rcS --num-cpus=2 --caches  
--kernel=/home/user1/simulators/gem5/FS/binaries/x86-4.8.13.smp
--disk-image=/home/user1/simulators/gem5/FS/disks/x86-security.img

*The execution stuck after the last line of the following output:*

      x86: Booting SMP configuration:
.... node  #0, CPUs:      #1
CPU: CPU feature xsave disabled, no CPUID level 0xd
x86: Booted up 1 node, 2 CPUs
smpboot: Total of 2 processors activated (31999.69 BogoMIPS)
devtmpfs: initialized
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns:
1911260446275000 ns
NET: Registered protocol family 16
cpuidle: using governor ladder
PCI: Using configuration type 1 for base access HugeTLB registered 2 MB page 
size, pre-allocated 0 pages
ACPI: Interpreter disabled.
vgaarb: loaded
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
pps_core: LinuxPPS API ver. 1 registered
pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti < 
giome...@linux.it> PTP clock support registered
PCI: Probing PCI hardware
PCI host bridge to bus 0000:00
pci_bus 0000:00: root bus resource [io  0x0000-0xffff] pci_bus 0000:00: root 
bus resource [mem 0x00000000-0xffffffffffff] pci_bus 0000:00: No busn resource 
found for root bus, will use [bus 00-ff] pci 0000:00:04.0: legacy IDE quirk: 
reg 0x10: [io  0x01f0-0x01f7] pci 0000:00:04.0: legacy IDE quirk: reg 0x14: [io 
 0x03f6] pci 0000:00:04.0: legacy IDE quirk: reg 0x18: [io  0x0170-0x0177] pci 
0000:00:04.0: legacy IDE quirk: reg 0x1c: [io  0x0376]

--000000000000c32c3b05ad5e1b5c
Content-Type: text/html; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

<div dir=3D"auto"><div style=3D"font-family:sans-serif;font-size:12.8px" di= 
r=3D"auto"><br></div><div style=3D"font-family:sans-serif;font-size:12.8px"=
 dir=3D"auto">Dear All,</div><span style=3D"font-family:sans-serif;font-siz=
e:12.8px">=C2=A0 I am trying to boot gem5 in FS mode for multiple cores. Ho= 
wever, I am facing a problem as mentioned below:</span><div style=3D"font-f= 
amily:sans-serif;font-size:12.8px" dir=3D"auto"><ol><li>Atomic CPU - workin= g 
properly.</li><li>TimingSimpleCPU - Single core - working properly.</li><=
li>TimingSimpleCPU - multiple cores (2 or 4) - the execution=C2=A0stuck
li>aft=
er partial booting.</li></ol><div><b>Please let me know=C2=A0where I am doi= 
ng=C2=A0the=C2=A0mistake. The commans=C2=A0I am using is:</b></div><div><b>= 
<br></b></div><div>&gt;build/X86/gem5.fast configs/example/fs.py --cpu-type= 
=3DTimingSimpleCPU --script=3D/home/user1/simulators/gem5/FS/runs.rcS --num=
-cpus=3D2 --caches =C2=A0--kernel=3D/home/user1/simulators/gem5/FS/binaries=
/x86-4.8.13.smp --disk-image=3D/home/user1/simulators/gem5/FS/disks/x86-sec=
urity.img<br></div><div><br></div><div><b>The execution stuck after the las= t 
line of the following output:</b></div><div><br></div><div>=C2=A0 =C2=A0 =
=C2=A0 x86: Booting SMP configuration:</div>.... node =C2=A0#0, CPUs: =C2=
=A0 =C2=A0 =C2=A0#1<br>CPU: CPU feature xsave disabled, no CPUID level 0xd<=
br>x86: Booted up 1 node, 2 CPUs<br>smpboot: Total of 2 processors
br>activate=
d (31999.69 BogoMIPS)<br>devtmpfs: initialized<br>clocksource: jiffies: mas=
k: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns<br>N=
ET: Registered protocol family 16<br>cpuidle: using governor ladder<br>PCI:=  
Using configuration type 1 for base access<br>HugeTLB registered 2 MB page=  
size, pre-allocated 0 pages<br>ACPI: Interpreter disabled.<br>vgaarb: load= 
ed<br>SCSI subsystem initialized<br>usbcore: registered new interface drive= r 
usbfs<br>usbcore: registered new interface driver hub<br>usbcore: registe= red 
new device driver usb<br>pps_core: LinuxPPS API ver. 1 registered<br>pp=
s_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti &lt;<a h= 
ref=3D"mailto:giome...@linux.it"; style=3D"text-decoration-line:none;color:r=
gb(66,133,244)">giome...@linux.it</a>&gt;<br>PTP clock support registered<b=
r>PCI: Probing PCI hardware<br>PCI host bridge to bus 0000:00<br>pci_bus
r>00=
00:00: root bus resource [io =C2=A00x0000-0xffff]<br>pci_bus 0000:00: root = 
bus resource [mem 0x00000000-0xffffffffffff]<br>pci_bus 0000:00: No busn re= 
source found for root bus, will use [bus 00-ff]<br>pci 0000:00:04.0: legacy=  
IDE quirk: reg 0x10: [io =C2=A00x01f0-0x01f7]<br>pci 0000:00:04.0: legacy = IDE 
quirk: reg 0x14: [io =C2=A00x03f6]<br>pci 0000:00:04.0: legacy IDE quir=
k: reg 0x18: [io =C2=A00x0170-0x0177]<br>pci 0000:00:04.0: legacy IDE quirk=
: reg 0x1c: [io =C2=A00x0376]</div></div>

--000000000000c32c3b05ad5e1b5c--

------------------------------

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