I am starting to learn gem5 using the Learning Gem5 book, and encountered this issue while implementing a non-blocking cache.
Logic at the cache in case of a miss is to send the demand request for the miss, and conditionally evict a block back to memory (writeback request). Now, these two requests cannot be sent in the same cycle since only a single packet can be sent in a single port in any cycle. Scheduling the eviction request to a later cycle might contend for the port with demand requests in the future, so that solution might not work as well. Queueing up eviction requests and writing them back as and when the port is free is IMO the best solution, implemented in modern processors as well. While this might very much be already present in gem5, I'm really missing out on where I could find it. It will be helpful if any leads to how contention of resources is handled in gem5, in general, can be provided. _______________________________________________ gem5-users mailing list -- [email protected] To unsubscribe send an email to [email protected] %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
