Hi all, While experimenting with gem5 classic cache, I tried to find out how an access miss is handled and with what latency.
Even if in *cache/tags/base_set_assoc.hh*, the access (here a miss) handling latency *"lat"* gets assigned to the *"lookupLatency"*, the actual latency that is used to handle a miss (in *cache/base.cc: handleTimingReqMiss( )* method) is the *"forwardLatency"*. This is my observation. Both *"lookupLatency"* and *"forwardLatency"* are assigned to the cache *"tag_latency"*, which is okay! But I experimented with different values for them and observed that the value of *"forwardLatency"* actually gets reflected ( in terms of the clock cycle delay from the *cpu_side* port to the *mem_side* port) into the system for handling a cache miss. Could someone please confirm whether my observation and understanding is correct or not? Regards, Aritra
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