[gem5-users] XBar on dcache port impacting BW?

[fisher.xue--- via gem5-users]

I am trying to connect the L1D to the CPU dcache port over an XBar (I intend to 
connect another memory to this XBar), however, when making this connection, I 
observe that the bandwidth to my L1 halves due  to XBar contention, however, I 
am modelling this as a 0-latency XBar with effectively infinite width. Does 
anyone have any idea what I could be doing wrong?
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