Hi all, I am running full system simulation with MESI_Three_Level protocol. The protocol (maybe other protocol also) provides transition count for each state and possible events in stats file. For example, STATE.EVENT tells how many state transition occured from STATE receiving EVENT. Also, the stats file shows demand hit/miss count for each level of cache controllers. The L2 cache controller in MESI_Three_Level profiles miss count with uu_profileHit when following transitions occur - NP.L1_GETS - NP.L1_GETS_INSTR - NP.L1_GETX - IS.L1_GETS - ISS.L1_GETS - MT.L1_GETX - MT.L1_GETS
However, when I sums all counts of above transition, it is far higher than deman miss count of L2 controller. The demand hit count also shows similar pattern. How can I interpret the results correctly? One more question is the transition counts of L0 and L1 cache controller looks somewhat like historgram. It shows the total count but it also shows something like historgram as below. system.ruby.L0Cache_Controller.S.Store | 83922 12.33% 12.33% | 100603 14.78% 27.11% | ... If the sampled value is latency, building histogram makes sense, but how can I interpret this for transition counts? Thanks, Daecheol.
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