Yeah, it does not seem like m5ops are implemented in RISC-V yet. I did not see any RISC-V specific code in "util/m5/src/abi/". One workaround could be to stop simulation at a particular instruction count (e.g. if you know at what instruction number your function of interest starts and ends) from the Python run script and dump stats. Please, note that there might be other (and better) ways to do this.
-Ayaz On Wed, Nov 25, 2020 at 9:37 PM Volkan Mutlu via gem5-users < gem5-users@gem5.org> wrote: > Hi Ayaz, > > Thank you so much for your answers, these definitely cleared things up a > bit. I'll try to look deeper in the code and see if I can navigate the > Python interface to adjust latencies. Also thanks for pointing out m5ops, I > was not aware. Though I wonder whether the documentation has not been > updated or if RISC-V has not been provided as a target ISA option for this > yet, I'll check that out as well. > > Best, > Volkan > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s >
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