Hi, I was trying to implement a baremetal OS for the RISCV architecture, that runs on gem5. I have a few doubts regarding the implementation of RISCV Interrupts in gem5.
1) The privileged ISA spec (section 3.1.6.1) says that : Interrupts for lower-privilege modes, w<x, are always globally disabled regardless of the setting of any global wIE bit for the lower-privilege mode. But when I checked the implementation in https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/arch/riscv/interrupts.hh , it seems this is not considered. std::bitset<NumInterruptTypes> globalMask() const { INTERRUPT mask = 0; STATUS status = tc->readMiscReg(MISCREG_STATUS); if (status.mie) mask.mei = mask.mti = mask.msi = 1; if (status.sie) mask.sei = mask.sti = mask.ssi = 1; if (status.uie) mask.uei = mask.uti = mask.usi = 1; return std::bitset<NumInterruptTypes>(mask); } should this function be something like this ? (or am I missing something?) std::bitset<NumInterruptTypes> globalMask(ThreadContext *tc) const { PrivilegeMode p = (PrivilegeMode)tc->readMiscReg(MISCREG_PRV); INTERRUPT mask = 0; STATUS status = tc->readMiscReg(MISCREG_STATUS); if (status.mie) mask.mei = mask.mti = mask.msi = 1; if (status.sie && (p == PRV_U || p == PRV_S)) mask.sei = mask.sti = mask.ssi = 1; if (status.uie && p == PRV_U) mask.uei = mask.uti = mask.usi = 1; return std::bitset<NumInterruptTypes>(mask); } 2) In the file https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/src/arch/riscv/faults.cc , in the following function : void RiscvFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) line 116 is status.mpie = status.sie; shouldn't this be status.mpie = status.mie; Can anyone please have a look, am I missing anything here ? Thanks, Deepak Mohan.
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