Makes sense! Feel free to post your contribution to gerrit once you manage to implement this. We would be very happy to have this merged in gem5
Kind Regards Giacomo > -----Original Message----- > From: POLYCHRONOU Nikolaos <nikolaos.polychro...@cea.fr> > Sent: 24 January 2021 20:43 > To: Giacomo Travaglini <giacomo.travagl...@arm.com>; gem5 users mailing > list <gem5-users@gem5.org> > Subject: RE: ARM PMU memory mapped registers > > Thank you very much for your response. > I expected that it is not implemented. I am not an expert but I think that > with > MRS/MSR instruction you only access the current cpu that you are. > What a would like to do is to monitor the pmus of one core using another core. > This is because of the overheads to interrupt the execution and read the > register values. > If I could succeed to read the pmu of a specific core from another core which > I > only use to reset and read the counters. > Thank you > > -----Original Message----- > From: Giacomo Travaglini <giacomo.travagl...@arm.com> > Sent: Sunday, January 24, 2021 7:05 PM > To: POLYCHRONOU Nikolaos <nikolaos.polychro...@cea.fr>; gem5 users > mailing list <gem5-users@gem5.org> > Subject: RE: ARM PMU memory mapped registers > > Hi Nikolaos > > > -----Original Message----- > > From: POLYCHRONOU Nikolaos <nikolaos.polychro...@cea.fr> > > Sent: 24 January 2021 10:38 > > To: gem5 users mailing list <gem5-users@gem5.org>; Giacomo Travaglini > > <giacomo.travagl...@arm.com> > > Subject: ARM PMU memory mapped registers > > > > Good morning to all, > > > > I would like to ask if anyone knows if PMU registers are memory mapped > > in the ROM. > > > > According the Arm Architecture Reference manual, PMUs are accessible via > two interfaces: > > - System Register interface (MSR/MRS instructions). This is mandatory and > *it's > currently the only supported interface in gem5* > - An optional external debug interface which optionally supports memory- > mapped accesses (note the two "optional") > > So the memory mapped implementation is regarded as an optional feature > meant to be used by an external debugger. > Nothing stops you from implementing it and using it for your own purpose > > I suggest you to have a look at chapter D7 of [1] > > > I instantiate 2 cpus in a full system model but I only see 1 > > instantiated PMU in the device tree, but normally I should see one PMU per > core. > > > > This is because multiple PMUs require a single node in the FDT. > You can see two PMUs are instantiated by checking the config.ini file. > > > I am not sure how to implement the memory mapped reading of PMUs , but > > before I try to implement sth in the simulator > > > > I would like to be sure that they exist in the current model. > > > > Thank you very much > > > > > > > > Nikolaos Foivos POLYCHRONOU > > > > PhD Student - Security of Embedded Systems/IoT/IIoT > > > > Département DSYS / LSOSP > > > > > > > > 17, rue des martyrs | 38000 Grenoble > > > > Fix work . +33 4 38 78 19 58 > > > > Office Bat. 4022 - P. 221 > > > > nikolaos.polychro...@cea.fr > > > > > > > > LETI, technology research institute > > > > Commissariat à l'énergie atomique et aux énergies alternatives > > > > www.leti.fr <http://www.leti.fr/> | LETI is a member of the Carnot > Institutes > > network > > > > > > > > > > > > > > > > <https://www.youtube.com/channel/UC3JgudJblGykrECv6OUhWFg> > > <https://twitter.com/cea_leti> <https://www.linkedin.com/company/leti> > > > > > > > > > > > > > > > [1]: https://developer.arm.com/documentation/ddi0487/latest/ > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, > please notify the sender immediately and do not disclose the contents to any > other person, use it for any purpose, or store or copy the information in any > medium. Thank you. IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
