Hi all,
I am running some simulations on sparse workloads in SE mode and, from what I understand looking at the code, there is no detailed simulation of address translation or page table walks in SE mode, but gem5 just keeps a map of virtual to physical addresses and uses it to provide the physical address. The map is not pre-populated and so page faults will still happen and trigger pipeline squashes, so page faults do have an impact on performance (due to the squash), but that's not really realistic because the page walk is not simulated. Please correct me if my understanding is wrong; in that case, the rest of this email might not make much sense 😊. For my experiments, I'm assuming the system will be set up with huge pages (1GB) to reduce the pressure on TLBs and study effects other than paging, so I wanted to reduce the squashes due to page faults from my simulations. What I found looking at the code is that, for ARM, the page size seems to be statically defined here: https://github.com/gem5/gem5/blob/stable/src/arch/arm/isa_traits.hh#L51 So, what I did is to change PageShift to 30 and rebuild gem5 and that seems to work. Now come the questions 😊 1. As far as I know, the ARM ISA should support at least three page sizes (4kB, 16kB, 64kB), but I can only see one page size defined in the code. Is there a plan to extend gem5 to support multiple page sizes? 2. I have only tested in SE mode for now, what happens in FS mode? Is there any support for huge pages? 3. Running experiments with different page sizes seems like a legit use case to me, would it make sense to make the page size become a parameter that can be changed without modifying the source code and recompiling gem5? Thanks! -- dbb
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