Hello,
we did a couple of investigations on the timing of Memory accesses in SE
mode (ARM CPU without L2 Cache + Memory in timing mode).
Using the DRAM- and Cache-Debug-Flags, we found the following relations
(see picture): The delay from the cache to the memory (Bus-to-Time) is
only a few ns, while the time back from the memory to the cache
(Bus-back-Time) is around 40ns. (The DRAM time is highly varying like
expected).
Now we are wondering, why one direction is over 30 times faster than the
other one?
Did we interpret some values from the debug-flags wrongly?
Thanks for your help.
-Flo
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