Dear community,
I would like to use the IGbE_e1000 card with RISC-V Linux Full System
Simulation. As I read in this link
(https://gem5.googlesource.com/public/gem5/+/refs/heads/stable/RELEASE-NOTES.md) gem5 v21.0 release includes RISC-V Full system Linux boot
support!
So, I contact Peter Yuen and he sends me the binaries, images,
bootloader etc. As a result, I simulate a Full Linux RISCV.
Specifically, I use the prebuilt files from here:
https://github.com/ppeetteerrs/gem5-RISC-V-FS-Linux/ (to be noticed
that following his instructions - Section 4, I build my own files and
working properly).
Here is the cmd: build/RISCV/gem5.opt -d $RISCV/logs
configs/example/riscv/fs_linux.py --kernel=$OUT/bbl --caches
--mem-size=256MB --mem-type=DDR4_2400_8x8 --cpu-type=AtomicSimpleCPU
--disk-image=$OUT/riscv_parsec_disk -n 1
However, as you can see in the file src/dev/riscv/HiFive.py there is
not implemented PCI interface yet. I try to add it in order to connect
the IGbE_e1000 ethernet card but I cannot achieve it. I do the
following:
1) Add the src/dev/riscv/pci_host.hh file:
#ifndef __DEV_RISCV_PCI_HOST_HH__
#define __DEV_RISCV_PCI_HOST_HH__
#include "dev/pci/host.hh"
struct GenericRiscvPciHostParams;
class GenericRiscvPciHost : public GenericPciHost
{
private:
int intBase;
public:
GenericRiscvPciHost(const GenericRiscvPciHostParams &p);
virtual ~GenericRiscvPciHost() {}
protected:
uint32_t mapPciInterrupt(const PciBusAddr &addr, PciIntPin pin)
const override;
};
#endif // __DEV_RISCV_PCI_HOST_HH__
2) Add the src/dev/riscv/pci_host.cc file:
#include "dev/riscv/pci_host.hh"
#include "params/GenericRiscvPciHost.hh"
GenericRiscvPciHost::GenericRiscvPciHost(const GenericRiscvPciHostParams &p)
: GenericPciHost(p), intBase(p.int_base)
{
}
uint32_t
GenericRiscvPciHost::mapPciInterrupt(
const PciBusAddr &addr, PciIntPin pin) const
{
return (intBase + (uint8_t)pin);
}
3) Add "Source('pci_host.cc')" to Sconscript
4) Add the following in the src/dev/riscv/HiFive.py
class GenericRiscvPciHost(GenericPciHost):
type = 'GenericRiscvPciHost'
cxx_header = "dev/riscv/pci_host.hh"
int_base = Param.Int(0x20,
"Base number used as interrupt line and PLIC source.")
5) Add in class HiFive(Platform):
pci_host = GenericRiscvPciHost(conf_base=0x30000000, conf_size='256MB',
conf_device_bits=12, pci_pio_base=0x2f000000)
ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
InterruptLine=1, InterruptPin=1)
6) Add in gem5/configs/example/riscv/fs_linux.py the following:
range_list = system.platform._off_chip_ranges()
range_list.append(AddrRange(0x2f000000, 0x5fffffff))
system.bridge.ranges = range_list
system.platform.pci_host.pio = system.iobus.mem_side_ports
system.platform.ethernet.host = system.platform.pci_host
system.platform.ethernet.pio = system.iobus.mem_side_ports
system.platform.ethernet.dma = system.iobus.cpu_side_ports
7) Add the following in the dts which is produced from auto
generateDeviceTree:
pci@30000000 {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <0x3>;
#size-cells = <0x2>;
#interrupt-cells = <0x1>;
reg = <0x0 0x30000000 0x0 0x10000000>;
ranges = <0x1000000 0x0 0x0 0x0 0x2f000000 0x0 0x10000 0x2000000
0x0 0x40000000 0x0 0x40000000 0x0 0x10000000>;
interrupt-map = <0x0 0x0 0x0 0x1 0x2 0x20 0x0 0x0 0x0 0x2 0x2 0x21
0x0 0x0 0x0 0x3 0x2 0x22 0x0 0x0 0x0 0x4 0x2 0x23 0x800 0x0 0x0 0x1
0x2 0x21 0x800 0x0 0x0 0x2 0x2 0x22 0x800 0x0 0x0 0x3 0x2 0x23 0x800
0x0 0x0 0x4 0x2 0x20 0x1000 0x0 0x0 0x1 0x2 0x22 0x1000 0x0 0x0 0x2
0x2 0x23 0x1000 0x0 0x0 0x3 0x2 0x20 0x1000 0x0 0x0 0x4 0x2 0x21
0x1800 0x0 0x0 0x1 0x2 0x23 0x1800 0x0 0x0 0x2 0x2 0x20 0x1800 0x0 0x0
0x3 0x2 0x21 0x1800 0x0 0x0 0x4 0x2 0x22>;
interrupt-map-mask = <0x1800 0x0 0x0 0xffffffff>;
dma-coherent;
bus-range = <0x0 0xff>;
linux,pci-domain = <0x0>;
};
However, when I try to connect the IGbE_e1000 I get:
panic: invalid access size(?) for PCI configspace!
I would appreciate it if anyone would like to help me please! :)
Best regards,
Nikolaos
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