Hi All:
When I simulate with the fastforward and maxinsts parameters in SE mod, I
only see sim_insts=my fastforward instructions in stats.txt after the maximum
number of instructions exits. The value of committedInsts is not always 0 in
switch_cpu.committedInsts, but if fastforward is removed, the value of
committedInsts is equal to the value of maxinsts.Why?
My cmd is : ./build/ARM/gem5.opt configs/example/se.py
--cpu-type=O3_ARM_1620 --cpu-clock=2.6GHz --sys-clock=2.6GHz --caches
--l1d_size=64kB --l1i_size=64kB --l2cache --l2_size=32MB --mem-size=32GB
--l3cache --nvmain-config=./nvmain_public/Config/DRAM_2933_64GB_2CH.config
--num-cpus=2 --fast-forward=10000000 -I 5000000 -c "./lat_mem_rd;./lat_mem_rd"
-o "-t 16 4096;-t 16 4096"
gem5 version 20.0.0.3
gem5 compiled May 7 2021 20:22:39
gem5 started May 7 2021 20:45:45
gem5 executing on ubuntu-kunpeng920-4, pid 393218
command line: ./build/ARM/gem5.opt configs/example/se.py --cpu-type=O3_ARM_1620
--cpu-clock=2.6GHz --sys-clock=2.6GHz --caches --l1d_size=64kB --l1i_size=64kB
--l2cache --l2_size=32MB --mem-size=32GB --l3cache
--nvmain-config=./nvmain_public/Config/DRAM_2933_64GB_2CH.config --num-cpus=2
--fast-forward=10000000 -I 5000000 -c './lat_mem_rd;./lat_mem_rd' -o '-t 16
4096;-t 16 4096'
Global frequency set at 1000000000000 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range
assigned (32768 Mbytes)
0: system.remote_gdb: listening for remote gdb on port 7000
0: system.remote_gdb: listening for remote gdb on port 7001
Switch at instruction count:10000000
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
info: Increasing stack size by one page.
"stride=4096
"stride=4096
Switched CPUS @ tick 3850626395
switching cpus
warn: PowerState: Already in the requested power state, request ignored
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
**** REAL SIMULATION ****
info: Entering event queue @ 3850626395. Starting simulation...
Exiting @ tick 3850626395 because a thread reached the max instruction count
gem5 End May 7 2021 20:46:12
final_tick 3850626395 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
host_inst_rate 761286818 #
Simulator instruction rate (inst/s)
host_mem_usage 34016560 #
Number of bytes of host memory used
host_op_rate 757203868 #
Simulator op (including micro ops) rate (op/s)
host_seconds 0.03 #
Real time elapsed on the host
host_tick_rate 0 #
Simulator tick rate (ticks/s)
sim_freq 1000000000000 #
Frequency of simulated ticks
sim_insts 20000002 #
Number of instructions simulated
sim_ops 20003100 #
Number of ops (including micro ops) simulated
sim_seconds 0 #
Number of seconds simulated
sim_ticks 0
system.cpu0.committedInsts 0 #
Number of instructions committed
system.cpu0.committedOps 0 #
Number of ops (including micro ops) committed
system.cpu1.committedInsts 0 #
Number of instructions committed
system.cpu1.committedOps 0 #
Number of ops (including micro ops) committed
system.switch_cpus0.commit.committedInsts 0 #
Number of instructions committed
system.switch_cpus0.commit.committedOps 0 #
Number of ops (including micro ops) committed
system.switch_cpus1.commit.committedInsts 0 #
Number of instructions committed
system.switch_cpus1.commit.committedOps 0 #
Number of ops (including micro ops) committed
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