Hi, I'm doing some experiments using gem5 FS mode for x86. In the FS mode I'm running a custom OS written for the requirements of my experiment. I have added a PIO device to the x86 system which responds to reads and writes to an address range. In the OS I have mapped this device to a range in the PCI memory map region (@3GB). I don't want this range to be cached, but when I add the cache hierarchy to my FS simulation it seems that the device range is also cached. I tried setting the C bit (Cache disable) in page table entries to prevent this device range from getting cached, but it seems that doesn't work. What can I do to prevent the address range of my device from being cached , or am I doing something conceptually wrong ? Any ideas / suggestions / pointers would be helpful.
Thanks, Deepak Mohan. _______________________________________________ gem5-users mailing list -- [email protected] To unsubscribe send an email to [email protected] %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
