Thank you .This is really useful.

On 2/11/21 15:51, Jason Lowe-Power via gem5-users wrote:
Hello,

Yes. MI_example and MESI_Two_Level have been tested with the RISC-V board in the components library. See https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/configs/example/components-library/riscv_fs.py

I am working on the CHI protocol. I have a WIP changeset that I could share. The final part I'm working on is getting DMA. That said, since MI_example and MESI_Two_Level work, there's evidence that any protocol should work.

Cheers,
Jason

On Tue, Nov 2, 2021 at 3:29 AM Javier Garcia Hernandez via gem5-users <gem5-users@gem5.org> wrote:

    Hello.

    Is Ruby supported on RISCV FS?
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