Good question, Felix! The short answer is that since there are instructions that take multiple cycles to execute you need something like a scoreboard to track the dependencies.
In the H&P book, you can see some details of this in Appendix C.5 (6th edition). If you happen to have the Patterson and Hennessy Computer Organization and Design book, Section 4.11 (2nd ed. of RISC-V version, titled "Real Stuff: The ARM Cortex-A53...") shows a pipeline very similar to the minor CPU. Cheers, Jason On Sat, Jan 29, 2022 at 4:06 PM Felix Böseler via gem5-users < gem5-users@gem5.org> wrote: > Hello everybody, > > According to [1] the gem5 minor CPU is an in-order processor model and > features a scoreboarding algorithm. However, according to [2] scoreboarding > is a dynamic scheduling algorithm with out-of-order execution like the > Tomasulo algorithm. Therefore, I have the following two questions: > > (1) Why is the minor CPU called an in-order CPU model if it has > scoreboarding capabilities? Is it because the issuing happens in-order, > nevertheless? > > (2) What is the difference between the O3 CPU model and the minor CPU > model if the minor CPU already has scoreboarding? Does the O3 CPU offers a > more sophisticated dynamic scheduling approach since [3] mentions register > renaming (as in the Tomasulo algorithm). > > Many regards and many thanks in advance > > Felix Böseler > > [1] https://www.gem5.org/documentation/general_docs/cpu_models/minor_cpu > > [2] Hennessy, John L.; Patterson, David A. (op. 2012): Computer > architecture. A quantitative approach. 5th ed. Waltham, MA: Morgan > Kaufmann/Elsevier. > > [3] https://www.gem5.org/documentation/general_docs/cpu_models/O3CPU > _______________________________________________ > gem5-users mailing list -- gem5-users@gem5.org > To unsubscribe send an email to gem5-users-le...@gem5.org > %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
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