Hi, I believe what you are trying to achieve is what is commonly called a "functional access". Though, I am not exactly sure about what is your intent when you say that you want to "bypass caches in order to maintain coherence" as it sounds contradictory to me.
If you chose to mix regular and cache-bypassing accesses to the same memory location without extra care, you will likely violate coherence and eventually face inconsistent data. The "extra care" usually consists in explicitly flushing caches to update main memory before bypassing the caches with subsequent accesses. If you only want to maintain coherence, then you have to perform "direct memory accesses" using the functional access of the regular gem5 ports. This will result in an instantaneous access to the data you are looking for, wherever the most up-to-date version of the data is, while updating the caches state to maintain coherence. Finally, if you really want to access main memory content and you really know what it can imply in terms of coherence violation, then you could directly connect your initiator to memory using an extra request port on the initiator side that you directly connect to the memory response port through a small XBar like the IOXBar. You will also have to bind to the XBar the port that was previously connected to the memory response port and the XBar output to memory. Don't forget to update the IOXBar default parameters to null latencies and the width to greater than cacheline size (likely 512 bits) in order not to introduce extra delays (it will still incur and extra clock cycle of delay, which is unlikely to cause any issue). Best, Gabriel _______________________________________________ gem5-users mailing list -- gem5-users@gem5.org To unsubscribe send an email to gem5-users-le...@gem5.org %(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
