Dear All,
I am trying to set the page table dirty bit Gem5 X86 *"pagetable_walker.cc"
(*/src/arch/x86*),* but using below code in the *stepWalk* function , I am
using TimingSimpleCPU.
*if(!pte.d && mode == BaseMMU::Write){ pte.d = 1;
doWrite = true; }*
But what I observed is that the *stepWalk* function is not getting write
mode access under TimingSimpleCPU . i.e. the condition I wrote to set the
dirty bit does not get satisfied in *stepWalk* because it is getting only
read mode access in TimingSimpleCPU.
If I am doing it at the wrong place, can someone please suggest the correct
way to set the dirty bit in the page table walker in the X86 system in Gem5.
Thanks
Arun KP
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