Dear gem5 community,I am trying to integrate DRAMsim3 with gem5, and I was able
to successfully build gem5 with DRAmsim3.And I can successfully use the full
system mode with AtomicSimple CPU. But when I use the TimingSimple CPU or
O3CPU, I can't get into the system.It reports a
bug:build/X86/sim/simulate.cc:194: info: Entering event queue @ 0. Starting
simulation... gem5.opt: build/X86/mem/dramsim3.cc:229: bool
gem5::memory::DRAMsim3::recvTimingReq(gem5::PacketPtr): Assertion
`wrapper.canAccept(pkt->getAddr(), pkt->isWrite())' failed. Program
aborted at tick 179728000And I use the following code to use the DRAMsim3 in
fs.py:
test_sys.mem_ctrls = [DRAMsim3()] test_sys.mem_ctrls[0].range =
AddrRange("0","2147483648") test_sys.mem_ctrls[0].configFile =
"ext/dramsim3/DRAMsim3/configs/DDR4_8Gb_x4_2666.ini" test_sys.mem_ctrls[0].port
= test_sys.membus.mem_side_ports
The gem5 version is 22.0.0.2. My Run Command is??./build/X86/gem5.opt
./configs/example/fs.py --cpu-type=TimingSimpleCPU --kernel=vmlinux-5.4.49
--disk-image=x86-ubuntu.img.Is there any way I can solve this problem?
Regards,tang.
????????????????
707396...@qq.com
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