Hi Giacomo, Got it, thanks for your reply.
Can you tell me what architecture or processor the default ARM configuration used in gem5'O3CPU is based on? Regards Hasueng 2023년 3월 6일 (월) 오후 7:01, Giacomo Travaglini <giacomo.travagl...@arm.com>님이 작성: > Hi Haseung, > > > > In Arm FP registers share the same storage with SIMD (Vector) registers, > so we usually refer to them as SIMD&FP registers. > > This is why in gem5 we don’t use the floating point register type and we > use the vector type only > > > > Kind Regards > > > > Giacomo > > > > *From: *봉하승 via gem5-users <gem5-users@gem5.org> > *Reply to: *The gem5 Users mailing list <gem5-users@gem5.org> > *Date: *Saturday, 4 March 2023 at 14:25 > *To: *"gem5-users@gem5.org" <gem5-users@gem5.org> > *Cc: *"hasu...@ajou.ac.kr" <hasu...@ajou.ac.kr> > *Subject: *[gem5-users] There is not 'IsFloating' in arm/operands.isa > > > > Hi, > > I'm trying to use gem5 to simulate SPEC2017's LBM. > > LBM is an FP workload, and the simulation shows that > "system.switch_cpus.commit.floating" is zero in stats.txt. > > As a result of a little search, it was confirmed that instructions such as > fadd and fsub were classified as 'isVector'. > > I wonder why fadd is not 'isFloating' but 'isVector'. And when classified > like this, is there any possibility of simulation error in inst_queue or > fu_pool? > If you know, please reply. > > Thanks, > > Haseung > IMPORTANT NOTICE: The contents of this email and any attachments are > confidential and may also be privileged. If you are not the intended > recipient, please notify the sender immediately and do not disclose the > contents to any other person, use it for any purpose, or store or copy the > information in any medium. Thank you. >
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