Hi all, I've been looking into the default MOESI CMP Directory Protocol, and it came to my attention that, regarding SM states in L1 Cache (Transient state during a Shared to Exclusive Upgrade due to a store miss), when a load arrives from the local core (which hits since the Cache is technically still in Shared state), the cache will return the old Shared Datablk as its load hit result. Will it cause incoherence issues in memory ordering between the core and the memory system, since the CPU commits the store first and then commit the load returning the old data, but the memory system sees the load hit finish first, and then see the GETX finish? Also I already speculate that such loads will probably not arrive at the L1 Cache controller, since it would be blocked or forwarded with newer data due to outstanding stores in the lsq or the mandatory queue. I'm just wondering if the cache protocol itself is solid in terms of request ordering. Thanks in advance! Zhang Zhiyuan 2023.3.22 -- 姓名：章志元 手机：17717877306 邮箱：zhiyuanzhan...@fudan.edu.cn
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