Hi Giacomo,
Thanks for your birlliant reply, giving me some insights! But there are
some problems.
For the ZCR_EL register, I try to read or write the value from the register. I
try to use the inline assembly, I use msr instruction. Then use the g++
-march=armv8-a+sve option to compile the test program, the result is there is
no register named ZCR_EL. Maybe I do some wrong operation, but I'm not sure.
The /proc/sys/abi/sve_default_vector_length file. I cannot find this file in
the image I use. And I try to get some advice by google. It seemed I did
not get the proper answer.
The prctl system call, I read the manual about the function. And I use the
system call in my test code. I use the -march=armv8-a+sve option, and I also
try -msve-vector-bits=1024 to compile the program. I can get a binary. But when
I run it in the gem5, it will produce a output like:
/lib/aarch64-linux-gnu/glibc.so.6:version 'GLIBC_2.34' not found (required by
./sve). The sve is the binary I compiled . Then I check the glibc version
in my simulator and host, it's 2.27. I try to install it by the source code in
the image, but I can not operate it correctly.
I think the methods you provide are useful and insightful. Maybe I do not
operate correctly. Is there some your suggestions?
Best regards,
Zhang Meng
等价无穷小
zhang...@foxmail.com
Original Email
Sender:"Giacomo Travaglini via gem5-users"< gem5-users@gem5.org >;
Sent Time:2023/4/20 17:30
To:"The gem5 Users mailing list"< gem5-users@gem5.org >;
Cc recipient:"等价无穷小"< zhang...@foxmail.com >;"Giacomo Travaglini"<
giacomo.travagl...@arm.com >;
Subject:[gem5-users] Re: gem5 SVE vectoe length
Hi Zhang,
That parameter configures the *maximum* (hardware constrained) vector length.
It is possible to choose a different (smaller) vector length for a process by
configuring the following registers
ZCR_EL1 [1]
ZCR_EL2 [2]
ZCR_EL3 [3]
So I believe the problem is that while you are properly setting up the gem5
parameter, those registers have been configured for a smaller vector length.
What happens if you change the vector length from the guest?
In Linux you can either change /proc/sys/abi/sve_default_vector_length
(requires root permission) or use the prctl syscall [4] (from your program)
with the PR_SVE_SET_VL flag.
Let me know if this works...
Kind Regards
Giacomo
[1]:
https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/ZCR-EL1--SVE-Control-Register--EL1-?lang=en
[2]:
https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/ZCR-EL2--SVE-Control-Register--EL2-?lang=en
[3]:
https://developer.arm.com/documentation/ddi0601/2020-12/AArch64-Registers/ZCR-EL3--SVE-Control-Register--EL3-?lang=en
[4]: https://man7.org/linux/man-pages/man2/prctl.2.html
On 20/04/2023 09:22, 等价无穷小 via gem5-users wrote:
Dear gem5 Community,
I hope this email finds you well. I am currently working on a project that
involves using ARM SVE in gem5 FS mode, and I have encountered a problem that I
would appreciate your help with.
While using the ARM SVE in gem5 FS mode, I added the command line parameter
"--param 'system.sve_vl = 16'" to specify the vector length. However, when I
tried to retrieve the system vector length using the SVE intrinsic svcntb(),
the result I obtained was a vector length of 256 bits. This is different from
the expected result based on the parameter I set.
I am unsure if I have missed any important steps or if there is an issue with
my configuration. I would be grateful if you could provide guidance on this
matter or point me to any relevant resources or examples that could help me
resolve the issue.
Thank you in advance for your assistance, and I look forward to your response.
Best regards,
Zhang Meng
等价无穷小
zhang...@foxmail.com
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